From: Drew Fustini <fustini@kernel.org>
To: Icenowy Zheng <uwu@icenowy.me>
Cc: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Michal Wilczynski <m.wilczynski@samsung.com>,
Yao Zi <ziyao@disroot.org>, Han Gao <rabenda.cn@gmail.com>,
linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/3] clk: thead: support changing DPU pixel clock rate
Date: Thu, 14 Aug 2025 17:32:22 -0700 [thread overview]
Message-ID: <aJ6AFttcM+jUHHQy@x1> (raw)
In-Reply-To: <20250813072702.2176993-3-uwu@icenowy.me>
On Wed, Aug 13, 2025 at 03:27:01PM +0800, Icenowy Zheng wrote:
> The DPU pixel clock rate corresponds to the required dot clock of the
> display mode, so it needs to be tweakable.
>
> Add support to change it, by adding generic divider setting code,
> arming the code to the dpu0/dpu1 clocks, and setting the pixel clock
> connected to the DPU (after a gate) to CLK_SET_RATE_PARENT to propagate
> it to the dividers.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> Changes in v2:
> - Dropped round_rate() because of deprecation.
> - Changed the logic of determine_rate() to early return if the divider
> could be changed.
>
> drivers/clk/thead/clk-th1520-ap.c | 64 ++++++++++++++++++++++++++++---
> 1 file changed, 59 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
> index 0b5458af8c550..b220a8ed22607 100644
> --- a/drivers/clk/thead/clk-th1520-ap.c
> +++ b/drivers/clk/thead/clk-th1520-ap.c
> @@ -55,6 +55,7 @@ struct ccu_gate {
>
> struct ccu_div {
> u32 enable;
> + u32 div_en;
> struct ccu_div_internal div;
> struct ccu_internal mux;
> struct ccu_common common;
> @@ -198,6 +199,56 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
> return rate;
> }
>
> +static int ccu_div_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + struct ccu_div *cd = hw_to_ccu_div(hw);
> + unsigned int val;
> +
> + if (cd->div_en)
> + return divider_determine_rate(hw, req, NULL,
> + cd->div.width, cd->div.flags);
> +
> + regmap_read(cd->common.map, cd->common.cfg0, &val);
> + val = val >> cd->div.shift;
> + val &= GENMASK(cd->div.width - 1, 0);
> + return divider_ro_determine_rate(hw, req, NULL, cd->div.width,
> + cd->div.flags, val);
> +}
> +
> +static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
This should line up with open parenthesis. Other than that nit:
Reviewed-by: Drew Fustini <fustini@kernel.org>
If no other issues arise on this series, then I can just fix it up when
applying.
Thanks,
Drew
next prev parent reply other threads:[~2025-08-15 0:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-13 7:26 [PATCH v2 0/3] clk: thead: Changes to TH1520 clock driver for disp Icenowy Zheng
2025-08-13 7:27 ` [PATCH v2 1/3] clk: thead: add support for enabling/disabling PLLs Icenowy Zheng
2025-08-15 0:19 ` Drew Fustini
2025-08-13 7:27 ` [PATCH v2 2/3] clk: thead: support changing DPU pixel clock rate Icenowy Zheng
2025-08-15 0:32 ` Drew Fustini [this message]
2025-08-15 2:23 ` Troy Mitchell
2025-08-15 3:27 ` Icenowy Zheng
2025-08-13 7:27 ` [PATCH v2 3/3] clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL Icenowy Zheng
2025-08-15 0:36 ` Drew Fustini
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