[PATCH v3 0/8] Add clock support for Loongson 2K0300 SoC

[PATCH v3 0/8] Add clock support for Loongson 2K0300 SoC

[Yao Zi]

This series adds support for Loongson 2K0300's clock controller.
Loongson 2 clock driver is prepared to support more clock variants and
its flexibility is improved. All clock hardwares except the output one
for GMAC module are then defined.

A clock tree dump could be obtained here[1]. This series depends on v3
of series "Initial support for CTCISZ Forever Pi"[2] to apply.

Krzysztof, sorry I don't fully understand your comments in v2, I've
asked once again later[3] but got no reply, thus sent this new version
with my current understanding. I'm willing to hear from you more on the
binding issue, thanks.

[1]: https://gist.github.com/ziyao233/f7c4edcfbc1d6b325c71117af7233cc2
[2]: https://lore.kernel.org/all/20250523095408.25919-1-ziyao@disroot.org/
[3]: https://lore.kernel.org/all/aHB3Wvu-CVlYzhU7@pie.lan/

Changed from v2:
- Disallow clock-names property for loongson,2k0300-clk's binding, avoid
  overriding content of clock-names property within an allOf block
- Correct clock-controller's MMIO-region size in SoC devicetree
- Link to v2: https://lore.kernel.org/all/20250617162426.12629-1-ziyao@disroot.org/

Changed from v1:
- Fold loongson,ls2k0300-clk.yaml into loongson,ls2k-clk.yaml
- Include the new binding header in MAINTAINERS
- Link to v1: https://lore.kernel.org/all/20250523104552.32742-1-ziyao@disroot.org/

Yao Zi (8):
  dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible
  clk: loongson2: Allow specifying clock flags for gate clock
  clk: loongson2: Support scale clocks with an alternative mode
  clk: loongson2: Allow zero divisors for dividers
  clk: loongson2: Avoid hardcoding firmware name of the reference clock
  clk: loongson2: Add clock definitions for Loongson 2K0300 SoC
  LoongArch: dts: Add clock tree for Loongson 2K0300
  LoongArch: dts: Remove clock-frquency from UART0 of CTCISZ Forever Pi

 .../bindings/clock/loongson,ls2k-clk.yaml     |  21 ++-
 MAINTAINERS                                   |   1 +
 .../dts/loongson-2k0300-ctcisz-forever-pi.dts |   1 -
 arch/loongarch/boot/dts/loongson-2k0300.dtsi  |  16 ++-
 drivers/clk/clk-loongson2.c                   | 124 +++++++++++++++---
 .../dt-bindings/clock/loongson,ls2k0300-clk.h |  54 ++++++++
 6 files changed, 189 insertions(+), 28 deletions(-)
 create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h

-- 
2.50.1

[PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible

[Yao Zi]

Document the clock controller shipped in Loongson 2K0300 SoC, which
generates various clock signals for SoC peripherals.

Differing from previous generations of SoCs, 2K0300 requires a 120MHz
external clock input, and a separate dt-binding header is used for
cleanness.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 .../bindings/clock/loongson,ls2k-clk.yaml     | 21 ++++++--
 MAINTAINERS                                   |  1 +
 .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++
 3 files changed, 72 insertions(+), 4 deletions(-)
 create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h

diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
index 4f79cdb417ab..47eb6c0f85bc 100644
--- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
@@ -16,6 +16,7 @@ description: |
 properties:
   compatible:
     enum:
+      - loongson,ls2k0300-clk
       - loongson,ls2k0500-clk
       - loongson,ls2k-clk  # This is for Loongson-2K1000
       - loongson,ls2k2000-clk
@@ -24,8 +25,7 @@ properties:
     maxItems: 1
 
   clocks:
-    items:
-      - description: 100m ref
+    maxItems: 1
 
   clock-names:
     items:
@@ -36,13 +36,26 @@ properties:
     description:
       The clock consumer should specify the desired clock by having the clock
       ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
-      for the full list of Loongson-2 SoC clock IDs.
+      and include/dt-bindings/clock/loongson,ls2k0300-clk.h for the full list of
+      Loongson-2 SoC clock IDs.
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: loongson,ls2k0300-clk
+    then:
+      properties:
+        clock-names: false
+    else:
+      required:
+        - clock-names
 
 required:
   - compatible
   - reg
   - clocks
-  - clock-names
   - '#clock-cells'
 
 additionalProperties: false
diff --git a/MAINTAINERS b/MAINTAINERS
index 4912b8a83bbb..7960e65d7dfc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14365,6 +14365,7 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
 F:	drivers/clk/clk-loongson2.c
 F:	include/dt-bindings/clock/loongson,ls2k-clk.h
+F:	include/dt-bindings/clock/loongson,ls2k0300-clk.h
 
 LOONGSON SPI DRIVER
 M:	Yinbo Zhu <zhuyinbo@loongson.cn>
diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
new file mode 100644
index 000000000000..5e8f7b2f33f2
--- /dev/null
+++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ */
+#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
+#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
+
+/* Derivied from REFCLK */
+#define LS2K0300_CLK_STABLE			0
+#define LS2K0300_PLL_NODE			1
+#define LS2K0300_PLL_DDR			2
+#define LS2K0300_PLL_PIX			3
+#define LS2K0300_CLK_THSENS			4
+
+/* Derived from PLL_NODE */
+#define LS2K0300_CLK_NODE_DIV			5
+#define LS2K0300_CLK_NODE_PLL_GATE		6
+#define LS2K0300_CLK_NODE_SCALE			7
+#define LS2K0300_CLK_NODE_GATE			8
+#define LS2K0300_CLK_GMAC_DIV			9
+#define LS2K0300_CLK_GMAC_GATE			10
+#define LS2K0300_CLK_I2S_DIV			11
+#define LS2K0300_CLK_I2S_SCALE			12
+#define LS2K0300_CLK_I2S_GATE			13
+
+/* Derived from PLL_DDR */
+#define LS2K0300_CLK_DDR_DIV			14
+#define LS2K0300_CLK_DDR_GATE			15
+#define LS2K0300_CLK_NET_DIV			16
+#define LS2K0300_CLK_NET_GATE			17
+#define LS2K0300_CLK_DEV_DIV			18
+#define LS2K0300_CLK_DEV_GATE			19
+
+/* Derived from PLL_PIX */
+#define LS2K0300_CLK_PIX_DIV			20
+#define LS2K0300_CLK_PIX_PLL_GATE		21
+#define LS2K0300_CLK_PIX_SCALE			22
+#define LS2K0300_CLK_PIX_GATE			23
+#define LS2K0300_CLK_GMACBP_DIV			24
+#define LS2K0300_CLK_GMACBP_GATE		25
+
+/* Derived from CLK_DEV */
+#define LS2K0300_CLK_USB_SCALE			26
+#define LS2K0300_CLK_USB_GATE			27
+#define LS2K0300_CLK_APB_SCALE			28
+#define LS2K0300_CLK_APB_GATE			29
+#define LS2K0300_CLK_BOOT_SCALE			30
+#define LS2K0300_CLK_BOOT_GATE			31
+#define LS2K0300_CLK_SDIO_SCALE			32
+#define LS2K0300_CLK_SDIO_GATE			33
+
+#define LS2K0300_CLK_GMAC_IN			34
+
+#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
-- 
2.50.1

[PATCH v3 2/8] clk: loongson2: Allow specifying clock flags for gate clock

[Yao Zi]

Some gate clocks need to be supplied with flags, e.g., it may be
required to specify CLK_IS_CRTICAL for CPU clocks.

Add a field to loongson2_clk_board_info for representing clock flags,
and specify it when registering gate clocks. A new helper macro,
CLK_GATE_FLAGS, is added to simplify definitions.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/clk/clk-loongson2.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index 27e632edd484..cc3fb13e770f 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -50,6 +50,7 @@ struct loongson2_clk_board_info {
 	const char *name;
 	const char *parent_name;
 	unsigned long fixed_rate;
+	unsigned long flags;
 	u8 reg_offset;
 	u8 div_shift;
 	u8 div_width;
@@ -105,6 +106,18 @@ struct loongson2_clk_board_info {
 		.bit_idx	= _bidx,			\
 	}
 
+#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx,	\
+		       _flags)					\
+	{							\
+		.id		= _id,				\
+		.type		= CLK_TYPE_GATE,		\
+		.name		= _name,			\
+		.parent_name	= _pname,			\
+		.reg_offset	= _offset,			\
+		.bit_idx	= _bidx,			\
+		.flags		= _flags			\
+	}
+
 #define CLK_FIXED(_id, _name, _pname, _rate)			\
 	{							\
 		.id		= _id,				\
@@ -332,7 +345,8 @@ static int loongson2_clk_probe(struct platform_device *pdev)
 							  &clp->clk_lock);
 			break;
 		case CLK_TYPE_GATE:
-			hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0,
+			hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name,
+						       p->flags,
 						       clp->base + p->reg_offset,
 						       p->bit_idx, 0,
 						       &clp->clk_lock);
-- 
2.50.1

[PATCH v3 3/8] clk: loongson2: Support scale clocks with an alternative mode

[Yao Zi]

Loongson 2K0300 and 2K1500 ship scale clocks with an alternative mode.
There's one mode bit in clock configuration register indicating the
operation mode.

When mode bit is unset, the scale clock acts the same as previous
generation of scale clocks. When it's set, a different equation for
calculating result frequency, Fout = Fin / (scale + 1), is used.

This patch adds frequency calculation support for the scale clock
variant. A helper macro, CLK_SCALE_MODE, is added to simplify
definitions.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/clk/clk-loongson2.c | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index cc3fb13e770f..bba97270376c 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -42,6 +42,7 @@ struct loongson2_clk_data {
 	u8 div_width;
 	u8 mult_shift;
 	u8 mult_width;
+	u8 bit_idx;
 };
 
 struct loongson2_clk_board_info {
@@ -96,6 +97,19 @@ struct loongson2_clk_board_info {
 		.div_width	= _dwidth,			\
 	}
 
+#define CLK_SCALE_MODE(_id, _name, _pname, _offset,		\
+		  _dshift, _dwidth, _midx)			\
+	{							\
+		.id		= _id,				\
+		.type		= CLK_TYPE_SCALE,		\
+		.name		= _name,			\
+		.parent_name	= _pname,			\
+		.reg_offset	= _offset,			\
+		.div_shift	= _dshift,			\
+		.div_width	= _dwidth,			\
+		.bit_idx	= _midx + 1,			\
+	}
+
 #define CLK_GATE(_id, _name, _pname, _offset, _bidx)		\
 	{							\
 		.id		= _id,				\
@@ -243,13 +257,18 @@ static const struct clk_ops loongson2_pll_recalc_ops = {
 static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
 						     unsigned long parent_rate)
 {
-	u64 val, mult;
+	u64 val, scale;
+	u32 mode = 0;
 	struct loongson2_clk_data *clk = to_loongson2_clk(hw);
 
 	val  = readq(clk->reg);
-	mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
+	scale = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
+
+	if (clk->bit_idx)
+		mode = val & BIT(clk->bit_idx - 1);
 
-	return div_u64((u64)parent_rate * mult, 8);
+	return mode == 0 ? div_u64((u64)parent_rate * scale, 8) :
+			   div_u64((u64)parent_rate, scale);
 }
 
 static const struct clk_ops loongson2_freqscale_recalc_ops = {
@@ -284,6 +303,7 @@ static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
 	clk->div_width	= cld->div_width;
 	clk->mult_shift	= cld->mult_shift;
 	clk->mult_width	= cld->mult_width;
+	clk->bit_idx	= cld->bit_idx;
 	clk->hw.init	= &init;
 
 	hw = &clk->hw;
-- 
2.50.1

[PATCH v3 4/8] clk: loongson2: Allow zero divisors for dividers

[Yao Zi]

Loongson 2K0300 and 2K0500 ship divider clocks which allows zero
divisors, in which case the divider acts the same as one is specified.

Let's pass CLK_DIVIDER_ALLOW_ZERO when registering divider clocks to
prepare for future introduction of these clocks.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/clk/clk-loongson2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index bba97270376c..7a916c7d2718 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -361,7 +361,8 @@ static int loongson2_clk_probe(struct platform_device *pdev)
 							  p->parent_name, 0,
 							  clp->base + p->reg_offset,
 							  p->div_shift, p->div_width,
-							  CLK_DIVIDER_ONE_BASED,
+							  CLK_DIVIDER_ONE_BASED |
+							  CLK_DIVIDER_ALLOW_ZERO,
 							  &clp->clk_lock);
 			break;
 		case CLK_TYPE_GATE:
-- 
2.50.1

[PATCH v3 5/8] clk: loongson2: Avoid hardcoding firmware name of the reference clock

[Yao Zi]

Loongson 2K0300 requires a reference clock with a frequency different
from previous SoCs (120MHz v.s. 100MHz), thus hardcoding the firmware
name of the reference clock as ref_100m isn't a good idea.

This patch retrives the clock name of the reference clock dynamically
during probe, avoiding the hardcoded pdata structure and preparing for
support of future SoCs.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/clk/clk-loongson2.c | 33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index 7a916c7d2718..52a9f1c2794a 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -13,10 +13,6 @@
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <dt-bindings/clock/loongson,ls2k-clk.h>
 
-static const struct clk_parent_data pdata[] = {
-	{ .fw_name = "ref_100m", },
-};
-
 enum loongson2_clk_type {
 	CLK_TYPE_PLL,
 	CLK_TYPE_SCALE,
@@ -275,7 +271,8 @@ static const struct clk_ops loongson2_freqscale_recalc_ops = {
 	.recalc_rate = loongson2_freqscale_recalc_rate,
 };
 
-static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
+static struct clk_hw *loongson2_clk_register(const char *parent,
+					     struct loongson2_clk_provider *clp,
 					     const struct loongson2_clk_board_info *cld,
 					     const struct clk_ops *ops)
 {
@@ -292,11 +289,7 @@ static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
 	init.ops   = ops;
 	init.flags = 0;
 	init.num_parents = 1;
-
-	if (!cld->parent_name)
-		init.parent_data = pdata;
-	else
-		init.parent_names = &cld->parent_name;
+	init.parent_names = &parent;
 
 	clk->reg	= clp->base + cld->reg_offset;
 	clk->div_shift	= cld->div_shift;
@@ -321,11 +314,17 @@ static int loongson2_clk_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct loongson2_clk_provider *clp;
 	const struct loongson2_clk_board_info *p, *data;
+	const char *refclk_name, *parent_name;
 
 	data = device_get_match_data(dev);
 	if (!data)
 		return -EINVAL;
 
+	refclk_name = of_clk_get_parent_name(dev->of_node, 0);
+	if (IS_ERR(refclk_name))
+		return dev_err_probe(dev, PTR_ERR(refclk_name),
+				     "failed to get refclk name\n");
+
 	for (p = data; p->name; p++)
 		clks_num = max(clks_num, p->id + 1);
 
@@ -347,18 +346,20 @@ static int loongson2_clk_probe(struct platform_device *pdev)
 
 	for (i = 0; i < clks_num; i++) {
 		p = &data[i];
+		parent_name = p->parent_name ? p->parent_name : refclk_name;
+
 		switch (p->type) {
 		case CLK_TYPE_PLL:
-			hw = loongson2_clk_register(clp, p,
+			hw = loongson2_clk_register(parent_name, clp, p,
 						    &loongson2_pll_recalc_ops);
 			break;
 		case CLK_TYPE_SCALE:
-			hw = loongson2_clk_register(clp, p,
+			hw = loongson2_clk_register(parent_name, clp, p,
 						    &loongson2_freqscale_recalc_ops);
 			break;
 		case CLK_TYPE_DIVIDER:
 			hw = devm_clk_hw_register_divider(dev, p->name,
-							  p->parent_name, 0,
+							  parent_name, 0,
 							  clp->base + p->reg_offset,
 							  p->div_shift, p->div_width,
 							  CLK_DIVIDER_ONE_BASED |
@@ -366,15 +367,15 @@ static int loongson2_clk_probe(struct platform_device *pdev)
 							  &clp->clk_lock);
 			break;
 		case CLK_TYPE_GATE:
-			hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name,
+			hw = devm_clk_hw_register_gate(dev, p->name, parent_name,
 						       p->flags,
 						       clp->base + p->reg_offset,
 						       p->bit_idx, 0,
 						       &clp->clk_lock);
 			break;
 		case CLK_TYPE_FIXED:
-			hw = devm_clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata,
-									 0, p->fixed_rate);
+			hw = devm_clk_hw_register_fixed_rate(dev, p->name, parent_name,
+							     0, p->fixed_rate);
 			break;
 		default:
 			return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
-- 
2.50.1

[PATCH v3 6/8] clk: loongson2: Add clock definitions for Loongson 2K0300 SoC

[Yao Zi]

The clock controller of Loongson 2K0300 consists of three PLLs, requires
an 120MHz external reference clock to function, and generates clocks in
various frequencies for SoC peripherals.

Clock definitions for previous SoC generations could be reused for most
clock hardwares. There're two gates marked as critical, clk_node_gate
and clk_boot_gate, which supply the CPU cores and the system
configuration bus. Disabling them leads to a SoC hang.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/clk/clk-loongson2.c | 48 +++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index 52a9f1c2794a..1d210a7683ea 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -12,6 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <dt-bindings/clock/loongson,ls2k-clk.h>
+#include <dt-bindings/clock/loongson,ls2k0300-clk.h>
 
 enum loongson2_clk_type {
 	CLK_TYPE_PLL,
@@ -137,6 +138,52 @@ struct loongson2_clk_board_info {
 		.fixed_rate	= _rate,			\
 	}
 
+static const struct loongson2_clk_board_info ls2k0300_clks[] = {
+	/* Reference Clock */
+	CLK_PLL(LS2K0300_PLL_NODE, "pll_node",   0x00, 15, 9, 8, 7),
+	CLK_PLL(LS2K0300_PLL_DDR,  "pll_ddr",    0x08, 15, 9, 8, 7),
+	CLK_PLL(LS2K0300_PLL_PIX,  "pll_pix",    0x10, 15, 9, 8, 7),
+	CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000),
+	CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000),
+	/* Node PLL */
+	CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
+	CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
+	CLK_DIV(LS2K0300_CLK_I2S_DIV,  "clk_i2s_div",  "pll_node", 0x04, 8, 7),
+	CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE,   "clk_node_pll_gate", "clk_node_div", 0x00, 0),
+	CLK_GATE(LS2K0300_CLK_GMAC_GATE,       "clk_gmac_gate",	    "clk_gmac_div", 0x00, 1),
+	CLK_GATE(LS2K0300_CLK_I2S_GATE,        "clk_i2s_gate",	    "clk_i2s_div", 0x00, 2),
+	CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate",	    "clk_node_scale",
+		       0x24, 0, CLK_IS_CRITICAL),
+	CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE,    "clk_node_scale",    "clk_node_pll_gate",
+		       0x20, 0, 3, 3),
+	/* DDR PLL */
+	CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7),
+	CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7),
+	CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7),
+	CLK_GATE(LS2K0300_CLK_NET_GATE,		"clk_net_gate", "clk_net_div", 0x08, 1),
+	CLK_GATE(LS2K0300_CLK_DEV_GATE,		"clk_dev_gate",	"clk_dev_div", 0x08, 2),
+	CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE,	"clk_ddr_gate",	"clk_ddr_div",
+		       0x08, 0, CLK_IS_CRITICAL),
+	/* PIX PLL */
+	CLK_DIV(LS2K0300_CLK_PIX_DIV,	 "clk_pix_div",	   "pll_pix", 0x10, 24, 7),
+	CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7),
+	CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate",	"clk_pix_div", 0x10, 0),
+	CLK_GATE(LS2K0300_CLK_PIX_GATE,	    "clk_pix_gate",	"clk_pix_scale", 0x24, 6),
+	CLK_GATE(LS2K0300_CLK_GMACBP_GATE,  "clk_gmacbp_gate",	"clk_gmacbp_div", 0x10, 1),
+	CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE,	"clk_pix_scale",	"clk_pix_pll_gate",
+		       0x20, 4, 3, 7),
+	/* clk_dev_gate */
+	CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, 24, 4),
+	CLK_GATE(LS2K0300_CLK_USB_GATE,	 "clk_usb_gate",	"clk_usb_scale", 0x24, 2),
+	CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate",	"clk_sdio_scale", 0x24, 4),
+	CLK_GATE(LS2K0300_CLK_APB_GATE,  "clk_apb_gate",	"clk_apb_scale", 0x24, 3),
+	CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate",	"clk_boot_scale",
+		       0x24, 1, CLK_IS_CRITICAL),
+	CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE,  "clk_usb_scale",  "clk_dev_gate", 0x20, 12, 3, 15),
+	CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE,  "clk_apb_scale",  "clk_dev_gate", 0x20, 16, 3, 19),
+	CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate", 0x20, 8, 3, 11),
+};
+
 static const struct loongson2_clk_board_info ls2k0500_clks[] = {
 	CLK_PLL(LOONGSON2_NODE_PLL,   "pll_node", 0,    16, 8, 8, 6),
 	CLK_PLL(LOONGSON2_DDR_PLL,    "pll_ddr",  0x8,  16, 8, 8, 6),
@@ -393,6 +440,7 @@ static int loongson2_clk_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id loongson2_clk_match_table[] = {
+	{ .compatible = "loongson,ls2k0300-clk", .data = &ls2k0300_clks },
 	{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
 	{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
 	{ .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
-- 
2.50.1

[PATCH v3 7/8] LoongArch: dts: Add clock tree for Loongson 2K0300

[Yao Zi]

Describe the clock controller integrated in Loongson 2K0300 SoC and
clocks for UARTs.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/loongarch/boot/dts/loongson-2k0300.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
index ce3574691aa9..d909a4eca312 100644
--- a/arch/loongarch/boot/dts/loongson-2k0300.dtsi
+++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/clock/loongson,ls2k0300-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -21,7 +22,7 @@ cpu0: cpu@0 {
 			compatible = "loongson,la264";
 			reg = <0>;
 			device_type = "cpu";
-			clocks = <&cpu_clk>;
+			clocks = <&clk LS2K0300_CLK_NODE_GATE>;
 		};
 
 	};
@@ -32,9 +33,10 @@ cpuintc: interrupt-controller {
 		#interrupt-cells = <1>;
 	};
 
-	cpu_clk: clock-1000m {
+	refclk: clock-120m {
 		compatible = "fixed-clock";
-		clock-frequency = <1000000000>;
+		clock-frequency = <120000000>;
+		clock-output-names = "refclk_120m";
 		#clock-cells = <0>;
 	};
 
@@ -46,6 +48,13 @@ soc@10000000 {
 			 <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>,
 			 <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>;
 
+		clk: clock-controller@16000400 {
+			compatible = "loongson,ls2k0300-clk";
+			reg = <0x0 0x16000400 0x0 0x30>;
+			clocks = <&refclk>;
+			#clock-cells = <1>;
+		};
+
 		liointc0: interrupt-controller@16001400 {
 			compatible = "loongson,liointc-2.0";
 			reg = <0x0 0x16001400 0x0 0x40>,
@@ -87,6 +96,7 @@ liointc1: interrupt-controller@16001440 {
 		uart0: serial@16100000 {
 			compatible = "ns16550a";
 			reg = <0 0x16100000 0 0x10>;
+			clocks = <&clk LS2K0300_CLK_APB_GATE>;
 			interrupt-parent = <&liointc0>;
 			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 			no-loopback-test;
-- 
2.50.1

[PATCH v3 8/8] LoongArch: dts: Remove clock-frquency from UART0 of CTCISZ Forever Pi

[Yao Zi]

The property isn't required anymore as the supply clock of UART0 has
been described.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts
index a033c086461f..1bdfff7fae92 100644
--- a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts
+++ b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts
@@ -40,6 +40,5 @@ linux,cma {
 };
 
 &uart0 {
-	clock-frequency = <100000000>;
 	status = "okay";
 };
-- 
2.50.1

Re: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible

[Krzysztof Kozlowski]

On Tue, Aug 05, 2025 at 03:01:40PM +0000, Yao Zi wrote:
> Document the clock controller shipped in Loongson 2K0300 SoC, which
> generates various clock signals for SoC peripherals.
> 
> Differing from previous generations of SoCs, 2K0300 requires a 120MHz
> external clock input, and a separate dt-binding header is used for
> cleanness.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  .../bindings/clock/loongson,ls2k-clk.yaml     | 21 ++++++--

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible

[Huacai Chen]

On Tue, Aug 5, 2025 at 11:03 PM Yao Zi <ziyao@disroot.org> wrote:
>
> Document the clock controller shipped in Loongson 2K0300 SoC, which
> generates various clock signals for SoC peripherals.
>
> Differing from previous generations of SoCs, 2K0300 requires a 120MHz
> external clock input, and a separate dt-binding header is used for
> cleanness.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  .../bindings/clock/loongson,ls2k-clk.yaml     | 21 ++++++--
>  MAINTAINERS                                   |  1 +
>  .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++
>  3 files changed, 72 insertions(+), 4 deletions(-)
>  create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> index 4f79cdb417ab..47eb6c0f85bc 100644
> --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> @@ -16,6 +16,7 @@ description: |
>  properties:
>    compatible:
>      enum:
> +      - loongson,ls2k0300-clk
>        - loongson,ls2k0500-clk
>        - loongson,ls2k-clk  # This is for Loongson-2K1000
>        - loongson,ls2k2000-clk
> @@ -24,8 +25,7 @@ properties:
>      maxItems: 1
>
>    clocks:
> -    items:
> -      - description: 100m ref
> +    maxItems: 1
>
>    clock-names:
>      items:
> @@ -36,13 +36,26 @@ properties:
>      description:
>        The clock consumer should specify the desired clock by having the clock
>        ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
> -      for the full list of Loongson-2 SoC clock IDs.
> +      and include/dt-bindings/clock/loongson,ls2k0300-clk.h for the full list of
> +      Loongson-2 SoC clock IDs.
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: loongson,ls2k0300-clk
> +    then:
> +      properties:
> +        clock-names: false
> +    else:
> +      required:
> +        - clock-names
>
>  required:
>    - compatible
>    - reg
>    - clocks
> -  - clock-names
>    - '#clock-cells'
>
>  additionalProperties: false
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4912b8a83bbb..7960e65d7dfc 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14365,6 +14365,7 @@ S:      Maintained
>  F:     Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
>  F:     drivers/clk/clk-loongson2.c
>  F:     include/dt-bindings/clock/loongson,ls2k-clk.h
> +F:     include/dt-bindings/clock/loongson,ls2k0300-clk.h
I think ls2k0300-clk.h can be merged into ls2k-clk.h

Huacai

>
>  LOONGSON SPI DRIVER
>  M:     Yinbo Zhu <zhuyinbo@loongson.cn>
> diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
> new file mode 100644
> index 000000000000..5e8f7b2f33f2
> --- /dev/null
> +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
> + */
> +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> +
> +/* Derivied from REFCLK */
> +#define LS2K0300_CLK_STABLE                    0
> +#define LS2K0300_PLL_NODE                      1
> +#define LS2K0300_PLL_DDR                       2
> +#define LS2K0300_PLL_PIX                       3
> +#define LS2K0300_CLK_THSENS                    4
> +
> +/* Derived from PLL_NODE */
> +#define LS2K0300_CLK_NODE_DIV                  5
> +#define LS2K0300_CLK_NODE_PLL_GATE             6
> +#define LS2K0300_CLK_NODE_SCALE                        7
> +#define LS2K0300_CLK_NODE_GATE                 8
> +#define LS2K0300_CLK_GMAC_DIV                  9
> +#define LS2K0300_CLK_GMAC_GATE                 10
> +#define LS2K0300_CLK_I2S_DIV                   11
> +#define LS2K0300_CLK_I2S_SCALE                 12
> +#define LS2K0300_CLK_I2S_GATE                  13
> +
> +/* Derived from PLL_DDR */
> +#define LS2K0300_CLK_DDR_DIV                   14
> +#define LS2K0300_CLK_DDR_GATE                  15
> +#define LS2K0300_CLK_NET_DIV                   16
> +#define LS2K0300_CLK_NET_GATE                  17
> +#define LS2K0300_CLK_DEV_DIV                   18
> +#define LS2K0300_CLK_DEV_GATE                  19
> +
> +/* Derived from PLL_PIX */
> +#define LS2K0300_CLK_PIX_DIV                   20
> +#define LS2K0300_CLK_PIX_PLL_GATE              21
> +#define LS2K0300_CLK_PIX_SCALE                 22
> +#define LS2K0300_CLK_PIX_GATE                  23
> +#define LS2K0300_CLK_GMACBP_DIV                        24
> +#define LS2K0300_CLK_GMACBP_GATE               25
> +
> +/* Derived from CLK_DEV */
> +#define LS2K0300_CLK_USB_SCALE                 26
> +#define LS2K0300_CLK_USB_GATE                  27
> +#define LS2K0300_CLK_APB_SCALE                 28
> +#define LS2K0300_CLK_APB_GATE                  29
> +#define LS2K0300_CLK_BOOT_SCALE                        30
> +#define LS2K0300_CLK_BOOT_GATE                 31
> +#define LS2K0300_CLK_SDIO_SCALE                        32
> +#define LS2K0300_CLK_SDIO_GATE                 33
> +
> +#define LS2K0300_CLK_GMAC_IN                   34
> +
> +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> --
> 2.50.1
>

Re: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible

[Yao Zi]

On Wed, Aug 06, 2025 at 04:36:50PM +0800, Huacai Chen wrote:
> On Tue, Aug 5, 2025 at 11:03 PM Yao Zi <ziyao@disroot.org> wrote:
> >
> > Document the clock controller shipped in Loongson 2K0300 SoC, which
> > generates various clock signals for SoC peripherals.
> >
> > Differing from previous generations of SoCs, 2K0300 requires a 120MHz
> > external clock input, and a separate dt-binding header is used for
> > cleanness.
> >
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  .../bindings/clock/loongson,ls2k-clk.yaml     | 21 ++++++--
> >  MAINTAINERS                                   |  1 +
> >  .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++
> >  3 files changed, 72 insertions(+), 4 deletions(-)
> >  create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h
> >

...

> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 4912b8a83bbb..7960e65d7dfc 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -14365,6 +14365,7 @@ S:      Maintained
> >  F:     Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> >  F:     drivers/clk/clk-loongson2.c
> >  F:     include/dt-bindings/clock/loongson,ls2k-clk.h
> > +F:     include/dt-bindings/clock/loongson,ls2k0300-clk.h
> I think ls2k0300-clk.h can be merged into ls2k-clk.h

Honestly I think a separate header makes the purpose more clear, and
follows the convention that name of binding header matches the
compatible, but I'm willing to change if you really consider merging
them together is better and dt-binding maintainer agrees on this.

> Huacai

Thanks,
Yao Zi

> >
> >  LOONGSON SPI DRIVER
> >  M:     Yinbo Zhu <zhuyinbo@loongson.cn>
> > diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
> > new file mode 100644
> > index 000000000000..5e8f7b2f33f2
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
> > @@ -0,0 +1,54 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> > +/*
> > + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
> > + */
> > +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> > +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> > +
> > +/* Derivied from REFCLK */
> > +#define LS2K0300_CLK_STABLE                    0
> > +#define LS2K0300_PLL_NODE                      1
> > +#define LS2K0300_PLL_DDR                       2
> > +#define LS2K0300_PLL_PIX                       3
> > +#define LS2K0300_CLK_THSENS                    4
> > +
> > +/* Derived from PLL_NODE */
> > +#define LS2K0300_CLK_NODE_DIV                  5
> > +#define LS2K0300_CLK_NODE_PLL_GATE             6
> > +#define LS2K0300_CLK_NODE_SCALE                        7
> > +#define LS2K0300_CLK_NODE_GATE                 8
> > +#define LS2K0300_CLK_GMAC_DIV                  9
> > +#define LS2K0300_CLK_GMAC_GATE                 10
> > +#define LS2K0300_CLK_I2S_DIV                   11
> > +#define LS2K0300_CLK_I2S_SCALE                 12
> > +#define LS2K0300_CLK_I2S_GATE                  13
> > +
> > +/* Derived from PLL_DDR */
> > +#define LS2K0300_CLK_DDR_DIV                   14
> > +#define LS2K0300_CLK_DDR_GATE                  15
> > +#define LS2K0300_CLK_NET_DIV                   16
> > +#define LS2K0300_CLK_NET_GATE                  17
> > +#define LS2K0300_CLK_DEV_DIV                   18
> > +#define LS2K0300_CLK_DEV_GATE                  19
> > +
> > +/* Derived from PLL_PIX */
> > +#define LS2K0300_CLK_PIX_DIV                   20
> > +#define LS2K0300_CLK_PIX_PLL_GATE              21
> > +#define LS2K0300_CLK_PIX_SCALE                 22
> > +#define LS2K0300_CLK_PIX_GATE                  23
> > +#define LS2K0300_CLK_GMACBP_DIV                        24
> > +#define LS2K0300_CLK_GMACBP_GATE               25
> > +
> > +/* Derived from CLK_DEV */
> > +#define LS2K0300_CLK_USB_SCALE                 26
> > +#define LS2K0300_CLK_USB_GATE                  27
> > +#define LS2K0300_CLK_APB_SCALE                 28
> > +#define LS2K0300_CLK_APB_GATE                  29
> > +#define LS2K0300_CLK_BOOT_SCALE                        30
> > +#define LS2K0300_CLK_BOOT_GATE                 31
> > +#define LS2K0300_CLK_SDIO_SCALE                        32
> > +#define LS2K0300_CLK_SDIO_GATE                 33
> > +
> > +#define LS2K0300_CLK_GMAC_IN                   34
> > +
> > +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> > --
> > 2.50.1
> >
> 

Re: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible

[Huacai Chen]

On Wed, Aug 6, 2025 at 8:30 PM Yao Zi <ziyao@disroot.org> wrote:
>
> On Wed, Aug 06, 2025 at 04:36:50PM +0800, Huacai Chen wrote:
> > On Tue, Aug 5, 2025 at 11:03 PM Yao Zi <ziyao@disroot.org> wrote:
> > >
> > > Document the clock controller shipped in Loongson 2K0300 SoC, which
> > > generates various clock signals for SoC peripherals.
> > >
> > > Differing from previous generations of SoCs, 2K0300 requires a 120MHz
> > > external clock input, and a separate dt-binding header is used for
> > > cleanness.
> > >
> > > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > > ---
> > >  .../bindings/clock/loongson,ls2k-clk.yaml     | 21 ++++++--
> > >  MAINTAINERS                                   |  1 +
> > >  .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++
> > >  3 files changed, 72 insertions(+), 4 deletions(-)
> > >  create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h
> > >
>
> ...
>
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 4912b8a83bbb..7960e65d7dfc 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -14365,6 +14365,7 @@ S:      Maintained
> > >  F:     Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
> > >  F:     drivers/clk/clk-loongson2.c
> > >  F:     include/dt-bindings/clock/loongson,ls2k-clk.h
> > > +F:     include/dt-bindings/clock/loongson,ls2k0300-clk.h
> > I think ls2k0300-clk.h can be merged into ls2k-clk.h
>
> Honestly I think a separate header makes the purpose more clear, and
> follows the convention that name of binding header matches the
> compatible, but I'm willing to change if you really consider merging
> them together is better and dt-binding maintainer agrees on this.
I think merging is better, because:
1, loongson,ls2k-clk.h has already contains ls2k500, ls2k1000,
ls2k2000, so ls2k300 is not special.
2, ls2k500, ls2k1000, ls2k2000 and ls2k300 use the same driver
(drivers/clk/clk-loongson2.c), it is not necessary to include two
headers.

And moreover, existing code uses NODE_PLL/DDR_PLL naming, ls2k300 uses
PLL_NODE/PLL_DDR is not so good.


Huacai

>
> > Huacai
>
> Thanks,
> Yao Zi
>
> > >
> > >  LOONGSON SPI DRIVER
> > >  M:     Yinbo Zhu <zhuyinbo@loongson.cn>
> > > diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
> > > new file mode 100644
> > > index 000000000000..5e8f7b2f33f2
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h
> > > @@ -0,0 +1,54 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> > > +/*
> > > + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
> > > + */
> > > +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> > > +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> > > +
> > > +/* Derivied from REFCLK */
> > > +#define LS2K0300_CLK_STABLE                    0
> > > +#define LS2K0300_PLL_NODE                      1
> > > +#define LS2K0300_PLL_DDR                       2
> > > +#define LS2K0300_PLL_PIX                       3
> > > +#define LS2K0300_CLK_THSENS                    4
> > > +
> > > +/* Derived from PLL_NODE */
> > > +#define LS2K0300_CLK_NODE_DIV                  5
> > > +#define LS2K0300_CLK_NODE_PLL_GATE             6
> > > +#define LS2K0300_CLK_NODE_SCALE                        7
> > > +#define LS2K0300_CLK_NODE_GATE                 8
> > > +#define LS2K0300_CLK_GMAC_DIV                  9
> > > +#define LS2K0300_CLK_GMAC_GATE                 10
> > > +#define LS2K0300_CLK_I2S_DIV                   11
> > > +#define LS2K0300_CLK_I2S_SCALE                 12
> > > +#define LS2K0300_CLK_I2S_GATE                  13
> > > +
> > > +/* Derived from PLL_DDR */
> > > +#define LS2K0300_CLK_DDR_DIV                   14
> > > +#define LS2K0300_CLK_DDR_GATE                  15
> > > +#define LS2K0300_CLK_NET_DIV                   16
> > > +#define LS2K0300_CLK_NET_GATE                  17
> > > +#define LS2K0300_CLK_DEV_DIV                   18
> > > +#define LS2K0300_CLK_DEV_GATE                  19
> > > +
> > > +/* Derived from PLL_PIX */
> > > +#define LS2K0300_CLK_PIX_DIV                   20
> > > +#define LS2K0300_CLK_PIX_PLL_GATE              21
> > > +#define LS2K0300_CLK_PIX_SCALE                 22
> > > +#define LS2K0300_CLK_PIX_GATE                  23
> > > +#define LS2K0300_CLK_GMACBP_DIV                        24
> > > +#define LS2K0300_CLK_GMACBP_GATE               25
> > > +
> > > +/* Derived from CLK_DEV */
> > > +#define LS2K0300_CLK_USB_SCALE                 26
> > > +#define LS2K0300_CLK_USB_GATE                  27
> > > +#define LS2K0300_CLK_APB_SCALE                 28
> > > +#define LS2K0300_CLK_APB_GATE                  29
> > > +#define LS2K0300_CLK_BOOT_SCALE                        30
> > > +#define LS2K0300_CLK_BOOT_GATE                 31
> > > +#define LS2K0300_CLK_SDIO_SCALE                        32
> > > +#define LS2K0300_CLK_SDIO_GATE                 33
> > > +
> > > +#define LS2K0300_CLK_GMAC_IN                   34
> > > +
> > > +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_
> > > --
> > > 2.50.1
> > >
> >
>

Re: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible

[Yanteng Si]

在 8/7/25 12:44 PM, Huacai Chen 写道:
> On Wed, Aug 6, 2025 at 8:30 PM Yao Zi <ziyao@disroot.org> wrote:
>>
>> On Wed, Aug 06, 2025 at 04:36:50PM +0800, Huacai Chen wrote:
>>> On Tue, Aug 5, 2025 at 11:03 PM Yao Zi <ziyao@disroot.org> wrote:
>>>>
>>>> Document the clock controller shipped in Loongson 2K0300 SoC, which
>>>> generates various clock signals for SoC peripherals.
>>>>
>>>> Differing from previous generations of SoCs, 2K0300 requires a 120MHz
>>>> external clock input, and a separate dt-binding header is used for
>>>> cleanness.
>>>>
>>>> Signed-off-by: Yao Zi <ziyao@disroot.org>
>>>> ---
>>>>   .../bindings/clock/loongson,ls2k-clk.yaml     | 21 ++++++--
>>>>   MAINTAINERS                                   |  1 +
>>>>   .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++
>>>>   3 files changed, 72 insertions(+), 4 deletions(-)
>>>>   create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h
>>>>
>>
>> ...
>>
>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>> index 4912b8a83bbb..7960e65d7dfc 100644
>>>> --- a/MAINTAINERS
>>>> +++ b/MAINTAINERS
>>>> @@ -14365,6 +14365,7 @@ S:      Maintained
>>>>   F:     Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
>>>>   F:     drivers/clk/clk-loongson2.c
>>>>   F:     include/dt-bindings/clock/loongson,ls2k-clk.h
>>>> +F:     include/dt-bindings/clock/loongson,ls2k0300-clk.h
>>> I think ls2k0300-clk.h can be merged into ls2k-clk.h
>>
>> Honestly I think a separate header makes the purpose more clear, and
>> follows the convention that name of binding header matches the
>> compatible, but I'm willing to change if you really consider merging
>> them together is better and dt-binding maintainer agrees on this.

> I think merging is better, because:
On this premise，pick my tag:

Reviewed-by: Yanteng Si <siyanteng@cqsoftware.com.cn>

Thanks,
Yanteng
> 1, loongson,ls2k-clk.h has already contains ls2k500, ls2k1000,
> ls2k2000, so ls2k300 is not special.
> 2, ls2k500, ls2k1000, ls2k2000 and ls2k300 use the same driver
> (drivers/clk/clk-loongson2.c), it is not necessary to include two
> headers.
> 
> And moreover, existing code uses NODE_PLL/DDR_PLL naming, ls2k300 uses
> PLL_NODE/PLL_DDR is not so good.
> 
> 
> Huacai
> 
>>
>>> Huacai
>>
>> Thanks,
>> Yao Zi
>>
>>>>
>>>>   LOONGSON SPI DRIVER
>>>>   M:     Yinbo Zhu <zhuyinbo@loongson.cn>
>>>> diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h

>>>> 2.50.1
>>>>
>>>
>>

Re: [PATCH v3 3/8] clk: loongson2: Support scale clocks with an alternative mode

[Huacai Chen]

Hi, Yao,

Can the subject line use "clk: loongson2: Allow ..." like Patch-2 and Patch-4?

Huacai

On Tue, Aug 5, 2025 at 11:04 PM Yao Zi <ziyao@disroot.org> wrote:
>
> Loongson 2K0300 and 2K1500 ship scale clocks with an alternative mode.
> There's one mode bit in clock configuration register indicating the
> operation mode.
>
> When mode bit is unset, the scale clock acts the same as previous
> generation of scale clocks. When it's set, a different equation for
> calculating result frequency, Fout = Fin / (scale + 1), is used.
>
> This patch adds frequency calculation support for the scale clock
> variant. A helper macro, CLK_SCALE_MODE, is added to simplify
> definitions.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  drivers/clk/clk-loongson2.c | 26 +++++++++++++++++++++++---
>  1 file changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
> index cc3fb13e770f..bba97270376c 100644
> --- a/drivers/clk/clk-loongson2.c
> +++ b/drivers/clk/clk-loongson2.c
> @@ -42,6 +42,7 @@ struct loongson2_clk_data {
>         u8 div_width;
>         u8 mult_shift;
>         u8 mult_width;
> +       u8 bit_idx;
>  };
>
>  struct loongson2_clk_board_info {
> @@ -96,6 +97,19 @@ struct loongson2_clk_board_info {
>                 .div_width      = _dwidth,                      \
>         }
>
> +#define CLK_SCALE_MODE(_id, _name, _pname, _offset,            \
> +                 _dshift, _dwidth, _midx)                      \
> +       {                                                       \
> +               .id             = _id,                          \
> +               .type           = CLK_TYPE_SCALE,               \
> +               .name           = _name,                        \
> +               .parent_name    = _pname,                       \
> +               .reg_offset     = _offset,                      \
> +               .div_shift      = _dshift,                      \
> +               .div_width      = _dwidth,                      \
> +               .bit_idx        = _midx + 1,                    \
> +       }
> +
>  #define CLK_GATE(_id, _name, _pname, _offset, _bidx)           \
>         {                                                       \
>                 .id             = _id,                          \
> @@ -243,13 +257,18 @@ static const struct clk_ops loongson2_pll_recalc_ops = {
>  static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
>                                                      unsigned long parent_rate)
>  {
> -       u64 val, mult;
> +       u64 val, scale;
> +       u32 mode = 0;
>         struct loongson2_clk_data *clk = to_loongson2_clk(hw);
>
>         val  = readq(clk->reg);
> -       mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
> +       scale = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
> +
> +       if (clk->bit_idx)
> +               mode = val & BIT(clk->bit_idx - 1);
>
> -       return div_u64((u64)parent_rate * mult, 8);
> +       return mode == 0 ? div_u64((u64)parent_rate * scale, 8) :
> +                          div_u64((u64)parent_rate, scale);
>  }
>
>  static const struct clk_ops loongson2_freqscale_recalc_ops = {
> @@ -284,6 +303,7 @@ static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
>         clk->div_width  = cld->div_width;
>         clk->mult_shift = cld->mult_shift;
>         clk->mult_width = cld->mult_width;
> +       clk->bit_idx    = cld->bit_idx;
>         clk->hw.init    = &init;
>
>         hw = &clk->hw;
> --
> 2.50.1
>

Re: [PATCH v3 6/8] clk: loongson2: Add clock definitions for Loongson 2K0300 SoC

[Huacai Chen]

Hi, Yao,

On Tue, Aug 5, 2025 at 11:05 PM Yao Zi <ziyao@disroot.org> wrote:
>
> The clock controller of Loongson 2K0300 consists of three PLLs, requires
> an 120MHz external reference clock to function, and generates clocks in
> various frequencies for SoC peripherals.
>
> Clock definitions for previous SoC generations could be reused for most
> clock hardwares. There're two gates marked as critical, clk_node_gate
> and clk_boot_gate, which supply the CPU cores and the system
> configuration bus. Disabling them leads to a SoC hang.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  drivers/clk/clk-loongson2.c | 48 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
>
> diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
> index 52a9f1c2794a..1d210a7683ea 100644
> --- a/drivers/clk/clk-loongson2.c
> +++ b/drivers/clk/clk-loongson2.c
> @@ -12,6 +12,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/io-64-nonatomic-lo-hi.h>
>  #include <dt-bindings/clock/loongson,ls2k-clk.h>
> +#include <dt-bindings/clock/loongson,ls2k0300-clk.h>
>
>  enum loongson2_clk_type {
>         CLK_TYPE_PLL,
> @@ -137,6 +138,52 @@ struct loongson2_clk_board_info {
>                 .fixed_rate     = _rate,                        \
>         }
>
> +static const struct loongson2_clk_board_info ls2k0300_clks[] = {
> +       /* Reference Clock */
> +       CLK_PLL(LS2K0300_PLL_NODE, "pll_node",   0x00, 15, 9, 8, 7),
> +       CLK_PLL(LS2K0300_PLL_DDR,  "pll_ddr",    0x08, 15, 9, 8, 7),
> +       CLK_PLL(LS2K0300_PLL_PIX,  "pll_pix",    0x10, 15, 9, 8, 7),
> +       CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000),
> +       CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000),
> +       /* Node PLL */
> +       CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
> +       CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
> +       CLK_DIV(LS2K0300_CLK_I2S_DIV,  "clk_i2s_div",  "pll_node", 0x04, 8, 7),
> +       CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE,   "clk_node_pll_gate", "clk_node_div", 0x00, 0),
> +       CLK_GATE(LS2K0300_CLK_GMAC_GATE,       "clk_gmac_gate",     "clk_gmac_div", 0x00, 1),
> +       CLK_GATE(LS2K0300_CLK_I2S_GATE,        "clk_i2s_gate",      "clk_i2s_div", 0x00, 2),
> +       CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate",     "clk_node_scale",
> +                      0x24, 0, CLK_IS_CRITICAL),
There is no 80 chars limit now, so feel free to define a clock in one line.

> +       CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE,    "clk_node_scale",    "clk_node_pll_gate",
> +                      0x20, 0, 3, 3),
The same.

> +       /* DDR PLL */
> +       CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7),
> +       CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7),
> +       CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7),
> +       CLK_GATE(LS2K0300_CLK_NET_GATE,         "clk_net_gate", "clk_net_div", 0x08, 1),
> +       CLK_GATE(LS2K0300_CLK_DEV_GATE,         "clk_dev_gate", "clk_dev_div", 0x08, 2),
> +       CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE,   "clk_ddr_gate", "clk_ddr_div",
> +                      0x08, 0, CLK_IS_CRITICAL),
The same.

> +       /* PIX PLL */
> +       CLK_DIV(LS2K0300_CLK_PIX_DIV,    "clk_pix_div",    "pll_pix", 0x10, 24, 7),
> +       CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7),
> +       CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x10, 0),
> +       CLK_GATE(LS2K0300_CLK_PIX_GATE,     "clk_pix_gate",     "clk_pix_scale", 0x24, 6),
> +       CLK_GATE(LS2K0300_CLK_GMACBP_GATE,  "clk_gmacbp_gate",  "clk_gmacbp_div", 0x10, 1),
> +       CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE,  "clk_pix_scale",        "clk_pix_pll_gate",
> +                      0x20, 4, 3, 7),
The same.

> +       /* clk_dev_gate */
> +       CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, 24, 4),
> +       CLK_GATE(LS2K0300_CLK_USB_GATE,  "clk_usb_gate",        "clk_usb_scale", 0x24, 2),
> +       CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate",       "clk_sdio_scale", 0x24, 4),
> +       CLK_GATE(LS2K0300_CLK_APB_GATE,  "clk_apb_gate",        "clk_apb_scale", 0x24, 3),
> +       CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate", "clk_boot_scale",
> +                      0x24, 1, CLK_IS_CRITICAL),
The same.

Huacai

> +       CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE,  "clk_usb_scale",  "clk_dev_gate", 0x20, 12, 3, 15),
> +       CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE,  "clk_apb_scale",  "clk_dev_gate", 0x20, 16, 3, 19),
> +       CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate", 0x20, 8, 3, 11),
> +};
> +
>  static const struct loongson2_clk_board_info ls2k0500_clks[] = {
>         CLK_PLL(LOONGSON2_NODE_PLL,   "pll_node", 0,    16, 8, 8, 6),
>         CLK_PLL(LOONGSON2_DDR_PLL,    "pll_ddr",  0x8,  16, 8, 8, 6),
> @@ -393,6 +440,7 @@ static int loongson2_clk_probe(struct platform_device *pdev)
>  }
>
>  static const struct of_device_id loongson2_clk_match_table[] = {
> +       { .compatible = "loongson,ls2k0300-clk", .data = &ls2k0300_clks },
>         { .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
>         { .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
>         { .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
> --
> 2.50.1
>

Re: [PATCH v3 6/8] clk: loongson2: Add clock definitions for Loongson 2K0300 SoC

[Yao Zi]

On Thu, Aug 07, 2025 at 07:21:32PM +0800, Huacai Chen wrote:
> Hi, Yao,
> 
> On Tue, Aug 5, 2025 at 11:05 PM Yao Zi <ziyao@disroot.org> wrote:
> >
> > The clock controller of Loongson 2K0300 consists of three PLLs, requires
> > an 120MHz external reference clock to function, and generates clocks in
> > various frequencies for SoC peripherals.
> >
> > Clock definitions for previous SoC generations could be reused for most
> > clock hardwares. There're two gates marked as critical, clk_node_gate
> > and clk_boot_gate, which supply the CPU cores and the system
> > configuration bus. Disabling them leads to a SoC hang.
> >
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  drivers/clk/clk-loongson2.c | 48 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 48 insertions(+)
> >
> > diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
> > index 52a9f1c2794a..1d210a7683ea 100644
> > --- a/drivers/clk/clk-loongson2.c
> > +++ b/drivers/clk/clk-loongson2.c
> > @@ -12,6 +12,7 @@
> >  #include <linux/platform_device.h>
> >  #include <linux/io-64-nonatomic-lo-hi.h>
> >  #include <dt-bindings/clock/loongson,ls2k-clk.h>
> > +#include <dt-bindings/clock/loongson,ls2k0300-clk.h>
> >
> >  enum loongson2_clk_type {
> >         CLK_TYPE_PLL,
> > @@ -137,6 +138,52 @@ struct loongson2_clk_board_info {
> >                 .fixed_rate     = _rate,                        \
> >         }
> >
> > +static const struct loongson2_clk_board_info ls2k0300_clks[] = {
> > +       /* Reference Clock */
> > +       CLK_PLL(LS2K0300_PLL_NODE, "pll_node",   0x00, 15, 9, 8, 7),
> > +       CLK_PLL(LS2K0300_PLL_DDR,  "pll_ddr",    0x08, 15, 9, 8, 7),
> > +       CLK_PLL(LS2K0300_PLL_PIX,  "pll_pix",    0x10, 15, 9, 8, 7),
> > +       CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000),
> > +       CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000),
> > +       /* Node PLL */
> > +       CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
> > +       CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
> > +       CLK_DIV(LS2K0300_CLK_I2S_DIV,  "clk_i2s_div",  "pll_node", 0x04, 8, 7),
> > +       CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE,   "clk_node_pll_gate", "clk_node_div", 0x00, 0),
> > +       CLK_GATE(LS2K0300_CLK_GMAC_GATE,       "clk_gmac_gate",     "clk_gmac_div", 0x00, 1),
> > +       CLK_GATE(LS2K0300_CLK_I2S_GATE,        "clk_i2s_gate",      "clk_i2s_div", 0x00, 2),
> > +       CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate",     "clk_node_scale",
> > +                      0x24, 0, CLK_IS_CRITICAL),
> There is no 80 chars limit now, so feel free to define a clock in one line.

Thanks, will merge definitions into a single line in the next version.

Best regards,
Yao Zi

Re: [PATCH v3 3/8] clk: loongson2: Support scale clocks with an alternative mode

[Yao Zi]

On Thu, Aug 07, 2025 at 07:18:33PM +0800, Huacai Chen wrote:
> Hi, Yao,
> 
> Can the subject line use "clk: loongson2: Allow ..." like Patch-2 and Patch-4?

Sorry, I don't get the point of rewording the subject... do you think
this looks more consistent?

I'd like to keep the original subject since scale clocks with
alternative operation mode are a relateively large feature, while PATCH
2 and 4 only introduces one member or appends a new flag.

To be honest, actually I don't really see a meaningful reason for
rewording...

> Huacai

Best regards,
Yao Zi

Re: [PATCH v3 3/8] clk: loongson2: Support scale clocks with an alternative mode

[Huacai Chen]

On Fri, Aug 8, 2025 at 11:24 AM Yao Zi <ziyao@disroot.org> wrote:
>
> On Thu, Aug 07, 2025 at 07:18:33PM +0800, Huacai Chen wrote:
> > Hi, Yao,
> >
> > Can the subject line use "clk: loongson2: Allow ..." like Patch-2 and Patch-4?
>
> Sorry, I don't get the point of rewording the subject... do you think
> this looks more consistent?
Yes, it seems Patch-2 and Patch-3 do similar things, but not a big deal.


Huacai

>
> I'd like to keep the original subject since scale clocks with
> alternative operation mode are a relateively large feature, while PATCH
> 2 and 4 only introduces one member or appends a new flag.
>
> To be honest, actually I don't really see a meaningful reason for
> rewording...
>
> > Huacai
>
> Best regards,
> Yao Zi