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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70da72cbff7sm108739796d6.62.2025.08.28.10.38.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 10:38:14 -0700 (PDT) Date: Thu, 28 Aug 2025 13:38:12 -0400 From: Brian Masney To: Ryan.Wanner@microchip.com Cc: mturquette@baylibre.com, sboyd@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, varshini.rajendran@microchip.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh@kernel.org Subject: Re: [PATCH v3 03/32] clk: at91: sam9x75: switch to parent_hw and parent_data Message-ID: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.14 (2025-02-20) On Thu, Jul 10, 2025 at 01:06:56PM -0700, Ryan.Wanner@microchip.com wrote: > From: Ryan Wanner > > Switch SAM9X75 clocks to use parent_hw and parent_data. Having > parent_hw instead of parent names improves to clock registration > speed and re-parenting. > > The USBCLK will be updated in subsequent patches that update the clock > registration functions to use parent_hw and parent_data. > > Signed-off-by: Ryan Wanner > --- > drivers/clk/at91/sam9x7.c | 308 +++++++++++++++++++++----------------- > 1 file changed, 173 insertions(+), 135 deletions(-) > > diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c > index cbb8b220f16b..31184e11165a 100644 > --- a/drivers/clk/at91/sam9x7.c > +++ b/drivers/clk/at91/sam9x7.c > + [PLL_COMPID_DIV1] = { > + .n = "plla_div2pmcck", > + .p = SAM9X7_PLL_PARENT_FRACCK, > + .l = &plladiv2_divpmc_layout, > + /* > + * This may feed critical parts of the system like timers. > + * It should not be disabled. > + */ > + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, > + .c = &plladiv2_characteristics, > + .eid = PMC_PLLADIV2, > + .t = PLL_TYPE_DIV, > + }, [snip] > - [PLL_ID_PLLA_DIV2] = { > - { > - .n = "plla_div2pmcck", > - .p = "plla_fracck", > - .l = &plladiv2_divpmc_layout, > - /* > - * This may feed critical parts of the system like timers. > - * It should not be disabled. > - */ > - .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, > - .c = &plladiv2_characteristics, > - .eid = PMC_PLLADIV2, > - .t = PLL_TYPE_DIV, > - }, > - }, Should the div2 to div1 rename be mentioned in the commit log? > @@ -710,32 +738,24 @@ static const struct { > static void __init sam9x7_pmc_setup(struct device_node *np) > { > struct clk_range range = CLK_RANGE(0, 0); > - const char *td_slck_name, *md_slck_name, *mainxtal_name; > + const char *main_xtal_name = "main_xtal"; > struct pmc_data *sam9x7_pmc; > const char *parent_names[9]; > void **clk_mux_buffer = NULL; > int clk_mux_buffer_size = 0; > - struct clk_hw *main_osc_hw; > struct regmap *regmap; > - struct clk_hw *hw; > + struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; > + struct clk_hw *td_slck_hw, *md_slck_hw, *usbck_hw; > + static struct clk_parent_data parent_data; > + struct clk_hw *parent_hws[9]; > int i, j; > > - i = of_property_match_string(np, "clock-names", "td_slck"); > - if (i < 0) > - return; > - > - td_slck_name = of_clk_get_parent_name(np, i); > - > - i = of_property_match_string(np, "clock-names", "md_slck"); > - if (i < 0) > - return; > - > - md_slck_name = of_clk_get_parent_name(np, i); > + td_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "td_slck")); > + md_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "md_slck")); > + main_xtal_hw = __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); Based on Stephen's comment on your earlier series, I think it would be worthwhile to call out that these __clk_get_hw() calls will be removed in later patches in this series. I know you do in the next patch. Everything else in this patch looks good to me. Brian