From: Brian Masney <bmasney@redhat.com>
To: "irving.ch.lin" <irving-ch.lin@mediatek.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Richard Cochran <richardcochran@gmail.com>,
Qiqi Wang <qiqi.wang@mediatek.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org,
netdev@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
sirius.wang@mediatek.com, vince-wl.liu@mediatek.com,
jh.hsu@mediatek.com
Subject: Re: [PATCH v4 04/21] clk: mediatek: Add MT8189 apmixedsys clock support
Date: Mon, 22 Dec 2025 13:00:36 -0500 [thread overview]
Message-ID: <aUmHRCXNy45PrVLG@redhat.com> (raw)
In-Reply-To: <20251215034944.2973003-5-irving-ch.lin@mediatek.com>
On Mon, Dec 15, 2025 at 11:49:13AM +0800, irving.ch.lin wrote:
> From: Irving-CH Lin <irving-ch.lin@mediatek.com>
>
> Add support for the MT8189 apmixedsys clock controller, which provides
> PLLs generated from SoC 26m.
>
> Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
> ---
> drivers/clk/mediatek/Kconfig | 13 ++
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 192 +++++++++++++++++++
^^^^^^^^^^^^^^^^^^^^^^^
This file, along with others in this series, is not listed in
MAINTAINERS. This is the current entry:
MEDIATEK MT6735 CLOCK & RESET DRIVERS
M: Yassine Oudjana <y.oudjana@protonmail.com>
L: linux-clk@vger.kernel.org
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c
F: drivers/clk/mediatek/clk-mt6735-imgsys.c
F: drivers/clk/mediatek/clk-mt6735-infracfg.c
F: drivers/clk/mediatek/clk-mt6735-mfgcfg.c
F: drivers/clk/mediatek/clk-mt6735-pericfg.c
F: drivers/clk/mediatek/clk-mt6735-topckgen.c
F: drivers/clk/mediatek/clk-mt6735-vdecsys.c
F: drivers/clk/mediatek/clk-mt6735-vencsys.c
F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h
F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h
F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h
F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
Should the entries to MAINTAINERS be simplified to the following?
F: drivers/clk/mediatek/
F: include/dt-bindings/clock/mediatek,*
Brian
next prev parent reply other threads:[~2025-12-22 18:00 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 3:49 [PATCH v4 00/21] Add support for MT8189 clock/power controller irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 01/21] dt-bindings: clock: mediatek: Add MT8189 clock definitions irving.ch.lin
2025-12-19 7:35 ` Krzysztof Kozlowski
2025-12-15 3:49 ` [PATCH v4 02/21] dt-bindings: power: mediatek: Add MT8189 power domain definitions irving.ch.lin
2025-12-19 7:36 ` Krzysztof Kozlowski
2025-12-19 7:42 ` Krzysztof Kozlowski
2025-12-15 3:49 ` [PATCH v4 03/21] clk: mediatek: clk-mux: Make sure bypass clk enabled while setting MFG rate irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 04/21] clk: mediatek: Add MT8189 apmixedsys clock support irving.ch.lin
2025-12-22 18:00 ` Brian Masney [this message]
2025-12-15 3:49 ` [PATCH v4 05/21] clk: mediatek: Add MT8189 topckgen " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 06/21] clk: mediatek: Add MT8189 vlpckgen " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 07/21] clk: mediatek: Add MT8189 vlpcfg " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 08/21] clk: mediatek: Add MT8189 bus " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 09/21] clk: mediatek: Add MT8189 cam " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 10/21] clk: mediatek: Add MT8189 dbgao " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 11/21] clk: mediatek: Add MT8189 dvfsrc " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 12/21] clk: mediatek: Add MT8189 i2c " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 13/21] clk: mediatek: Add MT8189 img " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 14/21] clk: mediatek: Add MT8189 mdp " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 15/21] clk: mediatek: Add MT8189 mfg " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 16/21] clk: mediatek: Add MT8189 dispsys " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 17/21] clk: mediatek: Add MT8189 scp " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 18/21] clk: mediatek: Add MT8189 ufs " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 19/21] clk: mediatek: Add MT8189 vcodec " irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 20/21] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin
2025-12-15 3:49 ` [PATCH v4 21/21] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin
2025-12-15 15:57 ` [PATCH v4 00/21] Add support for MT8189 clock/power controller Ulf Hansson
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