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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-88d9a63e296sm86625536d6.52.2025.12.22.10.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 10:00:39 -0800 (PST) Date: Mon, 22 Dec 2025 13:00:36 -0500 From: Brian Masney To: "irving.ch.lin" Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran , Qiqi Wang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, netdev@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, sirius.wang@mediatek.com, vince-wl.liu@mediatek.com, jh.hsu@mediatek.com Subject: Re: [PATCH v4 04/21] clk: mediatek: Add MT8189 apmixedsys clock support Message-ID: References: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> <20251215034944.2973003-5-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251215034944.2973003-5-irving-ch.lin@mediatek.com> User-Agent: Mutt/2.2.14 (2025-02-20) On Mon, Dec 15, 2025 at 11:49:13AM +0800, irving.ch.lin wrote: > From: Irving-CH Lin > > Add support for the MT8189 apmixedsys clock controller, which provides > PLLs generated from SoC 26m. > > Signed-off-by: Irving-CH Lin > --- > drivers/clk/mediatek/Kconfig | 13 ++ > drivers/clk/mediatek/Makefile | 1 + > drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 192 +++++++++++++++++++ ^^^^^^^^^^^^^^^^^^^^^^^ This file, along with others in this series, is not listed in MAINTAINERS. This is the current entry: MEDIATEK MT6735 CLOCK & RESET DRIVERS M: Yassine Oudjana L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c F: drivers/clk/mediatek/clk-mt6735-imgsys.c F: drivers/clk/mediatek/clk-mt6735-infracfg.c F: drivers/clk/mediatek/clk-mt6735-mfgcfg.c F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: drivers/clk/mediatek/clk-mt6735-vdecsys.c F: drivers/clk/mediatek/clk-mt6735-vencsys.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h Should the entries to MAINTAINERS be simplified to the following? F: drivers/clk/mediatek/ F: include/dt-bindings/clock/mediatek,* Brian