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From: Brian Masney <bmasney@redhat.com>
To: Conor Dooley <conor@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Claudiu Beznea <claudiu.beznea@tuxon.dev>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	kernel test robot <lkp@intel.com>
Subject: Re: [PATCH 0/3] clk: microchip: core: allow driver to be compiled with COMPILE_TEST
Date: Tue, 24 Feb 2026 12:27:27 -0500	[thread overview]
Message-ID: <aZ3ff9vq9yuCkwTQ@redhat.com> (raw)
In-Reply-To: <20260224-placate-runt-54aa8419ec40@spud>

On Tue, Feb 24, 2026 at 05:10:42PM +0000, Conor Dooley wrote:
> On Sun, Feb 22, 2026 at 06:51:03PM -0500, Brian Masney wrote:
> > Here's a small series that lets us enable COMPILE_TEST for the pic32 clk
> > driver so that this driver can be compiled on all architectures in the
> > future to help avoid breakage.
> 
> Why do you care about this platform? Originally I thought you cared cos
> you were getting involved in clock subsystem stuff, but I see you doing
> stuff with it in pinctrl etc. Is that just general cleanup work, or do
> you actually have an interest in the platform?

My sole interest is to clean up the clk driver, which spilled into
larger work to clean the include header to allow this driver to be
compiled on other architectures. If I was going to do this for the
clk driver, it wasn't that much work to do the other pic32 driver
cleanups while I was there.

Honestly, I hope to done with all of these pic32 drivers after what I
posted this week has been merged.

> Also, seeing "clk: microchip: core" in my inbox triggers me, cos the
> stuff I work on uses "microchip: core" a lot for FPGA IP cores. Can we
> do:
> 
> -- >8 --
> From 5e972ac119c87257ce141382019f2b58ebd53359 Mon Sep 17 00:00:00 2001
> From: Conor Dooley <conor.dooley@microchip.com>
> Date: Tue, 24 Feb 2026 16:59:53 +0000
> Subject: [PATCH] clk: microchip: rename clk-core to clk-pic32
> 
> clk-core is a confusingly generic name, since it is only used by a
> single platform and it uses very similar naming to the "soft" IP cores
> for use in FPGA fabric (CoreClock or similar is what that would be
> called, although nothing like that exists right now) that the FPGA
> business unit produces. Rename it to clk-pic32, matching the prefix
> used by most functions in the driver. As far as I can tell, impact
> on whatever users may (or may not...) exist for the platform is minimal
> as it's built-in only and the functions are called directly from
> clk-pic32mzda.c
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

That sounds good to me. Please post that as a separate patch.

Brian


  reply	other threads:[~2026-02-24 17:27 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-22 23:51 [PATCH 0/3] clk: microchip: core: allow driver to be compiled with COMPILE_TEST Brian Masney
2026-02-22 23:51 ` [PATCH 1/3] clk: microchip: core: update to use div64_ul() instead of do_div() Brian Masney
2026-02-23  9:09   ` David Laight
2026-02-24 16:56     ` Brian Masney
2026-02-24 22:50       ` David Laight
2026-02-22 23:51 ` [PATCH 2/3] clk: microchip: core: change asm nop calls to nop() Brian Masney
2026-02-22 23:51 ` [PATCH 3/3] clk: microchip: core: allow driver to be compiled with COMPILE_TEST Brian Masney
2026-02-24 17:10 ` [PATCH 0/3] " Conor Dooley
2026-02-24 17:27   ` Brian Masney [this message]
2026-02-24 17:36     ` Conor Dooley
2026-02-24 17:43       ` Brian Masney

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