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Wed, 25 Feb 2026 14:56:57 -0800 (PST) X-Received: by 2002:a05:690c:101:b0:796:4154:9fab with SMTP id 00721157ae682-7986ff520ddmr20295137b3.41.1772060216778; Wed, 25 Feb 2026 14:56:56 -0800 (PST) Received: from redhat.com ([2600:382:811f:bb35:ae9a:1ac7:e1d:86ce]) by smtp.gmail.com with ESMTPSA id 00721157ae682-79876ac3c0dsm1236297b3.12.2026.02.25.14.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 14:56:56 -0800 (PST) Date: Wed, 25 Feb 2026 17:56:53 -0500 From: Brian Masney To: Conor Dooley Cc: linux-clk@vger.kernel.org, stable@vger.kernel.org, Daire McNamara , Michael Turquette , Stephen Boyd , Claudiu Beznea , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] clk: microchip: mpfs-ccc: fix out of bounds access during output registration Message-ID: References: <20260224-briskly-scholar-294d13464721@wendy> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260224-briskly-scholar-294d13464721@wendy> User-Agent: Mutt/2.2.14 (2025-02-20) Hi Conor, On Tue, Feb 24, 2026 at 09:35:25AM +0000, Conor Dooley wrote: > UBSAN reported an out of bounds access during registration of the last > two outputs. This out of bounds access occurs because space is only > allocated in the hws array for two PLLs and the four output dividers > that each has, but the defined IDs contain two DLLS and their two > outputs each, which are not supported by the driver. The ID order is > PLLs -> DLLs -> PLL outputs -> DLL outputs. Decrement the PLL output IDs > by two while adding them to the array to avoid the problem. > > Fixes: d39fb172760e ("clk: microchip: add PolarFire SoC fabric clock support") > CC: stable@vger.kernel.org > Signed-off-by: Conor Dooley > --- > CC: Conor Dooley > CC: Daire McNamara > CC: Michael Turquette > CC: Stephen Boyd > CC: Claudiu Beznea > CC: linux-riscv@lists.infradead.org > CC: linux-clk@vger.kernel.org > CC: linux-kernel@vger.kernel.org > --- > drivers/clk/microchip/clk-mpfs-ccc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/microchip/clk-mpfs-ccc.c b/drivers/clk/microchip/clk-mpfs-ccc.c > index 3a3ea2d142f8a..54cfbb8be8ab5 100644 > --- a/drivers/clk/microchip/clk-mpfs-ccc.c > +++ b/drivers/clk/microchip/clk-mpfs-ccc.c > @@ -178,7 +178,7 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_ > return dev_err_probe(dev, ret, "failed to register clock id: %d\n", > out_hw->id); > > - data->hw_data.hws[out_hw->id] = &out_hw->divider.hw; > + data->hw_data.hws[out_hw->id - 2] = &out_hw->divider.hw; What happens when / if the DLLs are supported by this driver in the future? This seems like a trap for the future. According to include/dt-bindings/clock/microchip,mpfs-clock.h, there are only 16 clock IDs. Could hws be initialized to have enough room for all 16 structures, and would it be ok if it was a sparse array? At the very least, I think it would be nice to include a comment here. Brian