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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-899c7374600sm46063276d6.29.2026.02.27.07.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 07:01:03 -0800 (PST) Date: Fri, 27 Feb 2026 10:01:02 -0500 From: Brian Masney To: Geert Uytterhoeven Cc: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag Message-ID: References: <20260226-clk-det-rate-fw-managed-v1-0-4421dd2f6dc6@redhat.com> <20260226-clk-det-rate-fw-managed-v1-11-4421dd2f6dc6@redhat.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.14 (2025-02-20) Hi Geert, On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote: > On Thu, 26 Feb 2026 at 19:18, Brian Masney wrote: > > This clk driver has a noop determine_rate clk op. Drop this empty > > function, and enable the CLK_ROUNDING_FW_MANAGED flag. > > > > Signed-off-by: Brian Masney > > Thanks for your patch! > > > --- a/drivers/clk/renesas/rzg2l-cpg.c > > +++ b/drivers/clk/renesas/rzg2l-cpg.c > > @@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw, > > return pll5_rate; > > } > > > > -static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw, > > - struct clk_rate_request *req) > > -{ > > - return 0; > > -} > > - > > static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, > > unsigned long rate, > > unsigned long parent_rate) > > @@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, > > > > static const struct clk_ops rzg2l_cpg_sipll5_ops = { > > .recalc_rate = rzg2l_cpg_sipll5_recalc_rate, > > - .determine_rate = rzg2l_cpg_sipll5_determine_rate, > > .set_rate = rzg2l_cpg_sipll5_set_rate, > > }; > > > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core, > > init.name = core->name; > > parent_name = __clk_get_name(parent); > > init.ops = &rzg2l_cpg_sipll5_ops; > > - init.flags = 0; > > + init.flags = CLK_ROUNDING_FW_MANAGED; > > Iff this is the Right Thing To Do (TM), it needs a comment, as this > clock is not managed by firmware. Before I start a larger discussion on patch 1 with more people about a name for this flag, help me understand why this provider has a noop determine rate. Is the hardware eventually programmed with a rate that's close enough to what was passed in? Or it doesn't really matter what the clock rate is, just as long as it is running? Or should the determine_rate function be filled out in this particular case? Thanks, Brian