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Wed, 04 Mar 2026 14:21:27 -0800 (PST) Received: from redhat.com ([2600:382:7705:162f:3db4:e16a:e5d8:352e]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cbbf66b9d9sm1740582885a.12.2026.03.04.14.21.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 14:21:27 -0800 (PST) Date: Wed, 4 Mar 2026 17:21:23 -0500 From: Brian Masney To: Anirudh Srinivasan Cc: Drew Fustini , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, joel@jms.id.au, fustini@kernel.org, mpe@kernel.org, mpe@oss.tenstorrent.com, npiggin@oss.tenstorrent.com, agross@kernel.org, agross@oss.tenstorrent.com, Krzysztof Kozlowski Subject: Re: [PATCH v7 3/3] clk: tenstorrent: Add Atlantis clock controller driver Message-ID: References: <20260303-atlantis-clocks-v7-0-415c9dda086a@oss.tenstorrent.com> <20260303-atlantis-clocks-v7-3-415c9dda086a@oss.tenstorrent.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.2.14 (2025-02-20) Hi Anirudh, On Wed, Mar 04, 2026 at 11:53:38AM -0600, Anirudh Srinivasan wrote: > Sorry for the follow up, but wanted to run something by you. > > On Wed, Mar 4, 2026 at 10:40 AM Anirudh Srinivasan < > asrinivasan@oss.tenstorrent.com> wrote: > > > > Hello Brian, > > > > On Tue, Mar 3, 2026 at 4:32 PM Brian Masney wrote: > > > > > > Hi Anirudh, > > > > > > Thanks for the patch. A few minor comments below with some minor > > > nitpicks, additional places to use FIELD_GET(), plus some suggestions > > > for additional regmap helpers to use. > > > > > > > > > + > > > > +static int atlantis_clk_pll_is_enabled(struct clk_hw *hw) > > > > +{ > > > > + struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw); > > > > + u32 val, en_val, cg_val; > > > > + > > > > + regmap_read(pll->common.regmap, pll->config.reg_offset, &val); > > > > + regmap_read(pll->common.regmap, pll->config.en_reg_offset, > &en_val); > > > > + regmap_read(pll->common.regmap, pll->config.cg_reg_offset, > &cg_val); > > > > + > > > > + /* Check if PLL is powered on, locked, not bypassed and Gate > clk is enabled */ > > > > + return !!(en_val & PLL_CFG_EN_BIT) && !!(val & > PLL_CFG_LOCK_BIT) && > > > > + (!pll->config.cg_reg_enable || (cg_val & > pll->config.cg_reg_enable)) && > > > > + !(val & PLL_CFG_BYPASS_BIT); > > > > > > Could regmap_test_bits() make this a bit cleaner? > > > > > > > +} > > > > + > > > > +static int atlantis_clk_pll_enable(struct clk_hw *hw) > > > > +{ > > > > + struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw); > > > > + u32 val, en_val, cg_val; > > > > + int ret; > > > > + > > > > + regmap_read(pll->common.regmap, pll->config.reg_offset, &val); > > > > + regmap_read(pll->common.regmap, pll->config.en_reg_offset, > &en_val); > > > > + regmap_read(pll->common.regmap, pll->config.cg_reg_offset, > &cg_val); > > > > + > > > > + /* Check if PLL is already enabled, locked, not bypassed and > Gate clk is enabled */ > > > > + if ((en_val & PLL_CFG_EN_BIT) && (val & PLL_CFG_LOCK_BIT) && > > > > + (!pll->config.cg_reg_enable || (cg_val & > pll->config.cg_reg_enable)) && > > > > + !(val & PLL_CFG_BYPASS_BIT)) { > > > > > > Same about regmap_test_bits() here. > > > > These instances have it reading 3 different registers (unlike almost > > all the other examples that just read one) and testing bits across > > them. But I guess it should be possible to use test_bits here too. I > > will update them. > > This ends up becoming like this. > > static int atlantis_clk_pll_is_enabled(struct clk_hw *hw) > > { > > struct atlantis_clk_pll *pll = hw_to_atlantis_pll(hw); > > > > > /* Check if PLL is powered on, locked, not bypassed and Gate clk is > enabled */ > return regmap_test_bits(pll->common.regmap, pll->config.reg_offset, > PLL_CFG_LOCK_BIT) && > > regmap_test_bits(pll->common.regmap, > pll->config.en_reg_offset, PLL_CFG_EN_BIT) && > > regmap_test_bits(pll->common.regmap, > pll->config.cg_reg_offset, pll->config.cg_reg_enable) && > > !regmap_test_bits(pll->common.regmap, > pll->config.reg_offset, PLL_CFG_BYPASS_BIT); > > } > > We can't use a single call of regmap_test_bits to the > pll->config.reg_offset register cause we need to check if PLL_CFG_LOCK_BIT > is set and PLL_CFG_BYPASS_BIT is unset. We end up needing to make 2 reads > to that register. > > Any thoughts on whether I should still be using regmap_test_bits here? If it's not looking good in practice once you implement it, then just fall back to the older behavior. It was just a suggestion. I haven't used this yet, however there are also the regmap_field_xxx() helpers that are also available. drivers/clk/mstar/clk-msc313-mpll.c uses these helpers. I don't know if it would help to simplify your code. Brian