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Mon, 25 Nov 2024 03:34:53 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AP3YqMw018185 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 03:34:52 GMT Received: from nalasex01c.na.qualcomm.com (10.47.97.35) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 24 Nov 2024 19:34:52 -0800 Received: from nalasex01c.na.qualcomm.com ([fe80::5da8:4d0f:c16a:a1d]) by nalasex01c.na.qualcomm.com ([fe80::5da8:4d0f:c16a:a1d%11]) with mapi id 15.02.1544.009; Sun, 24 Nov 2024 19:34:51 -0800 From: "Renjiang Han (QUIC)" To: "bryan.odonoghue@linaro.org" , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Stanimir Varbanov , "Vikash Garodia (QUIC)" , Mauro Carvalho Chehab CC: "linux-arm-msm@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-media@vger.kernel.org" Subject: RE: [PATCH 2/2] venus: pm_helpers: Use dev_pm_genpd_set_hwmode to switch GDSC mode on V4 Thread-Topic: [PATCH 2/2] venus: pm_helpers: Use dev_pm_genpd_set_hwmode to switch GDSC mode on V4 Thread-Index: AQHbPMnJgtkyWgYmaE+y7I5Pm035ZbLDxuAAgAOLjvA= Date: Mon, 25 Nov 2024 03:34:51 +0000 Message-ID: References: <20241122-switch_gdsc_mode-v1-0-365f097ecbb0@quicinc.com> <20241122-switch_gdsc_mode-v1-2-365f097ecbb0@quicinc.com> <2299ec8f-4b80-48ea-96ed-d1eb40998e55@linaro.org> In-Reply-To: <2299ec8f-4b80-48ea-96ed-d1eb40998e55@linaro.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5-EJcI165nZ1WQSI8aZmFAeuN_JraGrV X-Proofpoint-ORIG-GUID: 5-EJcI165nZ1WQSI8aZmFAeuN_JraGrV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 impostorscore=0 priorityscore=1501 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 mlxlogscore=778 adultscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250028 On Friday, November 22, 2024 8:51 PM, Bryan O'Donoghue wrote: > On 22/11/2024 10:31, Renjiang Han wrote: > > - if (IS_V6(core)) > > + if (IS_V6(core) || IS_V4(core)) > sdm845 IS_V4() > The GDSCs for the clock OTOH are > static struct gdsc vcodec0_gdsc =3D { > .gdscr =3D 0x874, > .pd =3D { > .name =3D "vcodec0_gdsc", > }, > .cxcs =3D (unsigned int []){ 0x890, 0x930 }, > .cxc_count =3D 2, > .flags =3D HW_CTRL | POLL_CFG_GDSCR, > .pwrsts =3D PWRSTS_OFF_ON, > }; > static struct gdsc vcodec1_gdsc =3D { > .gdscr =3D 0x8b4, > .pd =3D { > .name =3D "vcodec1_gdsc", > }, > .cxcs =3D (unsigned int []){ 0x8d0, 0x950 }, > .cxc_count =3D 2, > .flags =3D HW_CTRL | POLL_CFG_GDSCR, > .pwrsts =3D PWRSTS_OFF_ON, > }; > I can't see how this series will work on 845. Thanks for your review. In [PATCH 1/2] clk: qcom: videocc: Use HW_CTRL_TRIG= GER flag for video GDSC's, the gdsc flag will be changed to HW_CTRL_TRIGGER= , so the v4 core also needs to use the method of switching GDSC mode like v= 6. > --- > bod Best Regards, Renjiang