From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C71362AEF1; Tue, 15 Apr 2025 05:25:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744694728; cv=none; b=UCBDExab1N2jaCUp0bYsOGGzoajYuf2xCEY4G91J2vhl2JMNgItyTLwKNuiciUiel2Lwnt6bHajMKYw4LA7dWsDM64LVS6X1mQQhwPFI3BLQVhSKMY6WzwASn+d/Cy2zY0bzn/1h1UDybZ/G9g71r+o8rg1/lfNUIT1SQbZW3+Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744694728; c=relaxed/simple; bh=3g0HtHucKV2ELg8L1hSRLVBf5I+pEyhtwCZI6HcaQg4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=qSFx4ee8/twYvwlfXJS1Yt16TElMRSTXHU+ktnRn3xuJipCII+9hKHQx5jAQBNqcJbKyfHpfQFsBmUHm6CiWL0sM1Rbsl1hI3Mgw3i/q+sZnyIKWWKc9xemCYmneYe9OIaHfJKQ95aDw+MDquFFzD0DloZCuSv5jiaGx7WSpHog= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Nhqqj8Q3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Nhqqj8Q3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6B74C4CEDD; Tue, 15 Apr 2025 05:25:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744694728; bh=3g0HtHucKV2ELg8L1hSRLVBf5I+pEyhtwCZI6HcaQg4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Nhqqj8Q3H0wMsFhCEbBr3e0Ck8+P5y8SUweVH2dePT8jyjphnZQ8+rmv9cf9fmspI bu2WPrtskV728ljnwnS003NI8xtnNiu6stEMfzCf3MOyrkiQ/ITWJ2qfm+PhyIMmB8 IVKrz6t8Kdzezv4/h90Ks7SrjmR7rMkod0C4CONDCUJwODfC/aL32G/lQqn2Rjac3G y/MvbWlGp2echnM/uyR4S1jfZwLYL6aP4z46GS7ukexLRrbm+ApG/UQZHgOxkgHori lc3aakjGmMX6206Jia0yE42lTa5/yi7Kv5PXg7Ivei0B11MXiJ5FtErxanG7FLtwVK kXexFD9AkolOw== Message-ID: Date: Tue, 15 Apr 2025 07:25:21 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 04/10] dt-bindings: clock: Add Qualcomm QCS615 Display clock controller To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20250414-qcs615-mm-v7-clock-controllers-v7-0-ebab8e3a96e9@quicinc.com> <20250414-qcs615-mm-v7-clock-controllers-v7-4-ebab8e3a96e9@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 14/04/2025 10:42, Taniya Das wrote: > + > +required: > + - compatible > + - reg Drop > + - clocks > + - '#clock-cells' Drop > + - '#reset-cells' Drop Please look at other bindings when writing yours. > + - '#power-domain-cells' > + > +allOf: > + - $ref: qcom,gcc.yaml# > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + clock-controller@af00000 { > + compatible = "qcom,qcs615-dispcc"; > + reg = <0x0af00000 0x20000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, > + <&mdss_dsi0_phy 0>, > + <&mdss_dsi0_phy 1>, > + <&mdss_dsi1_phy 0>, > + <&mdss_dp_phy 0>, > + <&mdss_dp_vco 0>; Drop excessive spaces before '0'. Best regards, Krzysztof