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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8a593ee25c9sm58197296d6.22.2026.04.03.07.44.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 07:44:50 -0700 (PDT) Date: Fri, 3 Apr 2026 10:44:47 -0400 From: Brian Masney To: Yu-Chun Lin Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, cylee12@realtek.com, afaerber@suse.com, jyanchou@realtek.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-realtek-soc@lists.infradead.org, james.tai@realtek.com, cy.huang@realtek.com, stanley_chang@realtek.com Subject: Re: [PATCH v6 04/10] clk: realtek: Add support for phase locked loops (PLLs) Message-ID: References: <20260402073957.2742459-1-eleanor.lin@realtek.com> <20260402073957.2742459-5-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260402073957.2742459-5-eleanor.lin@realtek.com> User-Agent: Mutt/2.3.0 (2026-01-25) Hi Cheng-Yu and Yu-Chun, On Thu, Apr 02, 2026 at 03:39:51PM +0800, Yu-Chun Lin wrote: > From: Cheng-Yu Lee > > Provide a full set of PLL operations for programmable PLLs and a read-only > variant for fixed or hardware-managed PLLs. > > Signed-off-by: Cheng-Yu Lee > Co-developed-by: Yu-Chun Lin > Signed-off-by: Yu-Chun Lin > --- > +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct clk_pll *clkp = to_clk_pll(hw); > + const struct freq_table *fv; > + int ret; > + > + fv = ftbl_find_by_rate(clkp->freq_tbl, rate); > + if (!fv || fv->rate != rate) > + return -EINVAL; > + > + if (clkp->seq_pre_set_freq) { > + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_pre_set_freq, > + clkp->num_seq_pre_set_freq); > + if (ret) > + return ret; > + } > + > + ret = regmap_update_bits(clkp->clkr.regmap, clkp->freq_reg, > + clkp->freq_mask, fv->val); > + if (ret) > + return ret; > + > + if (clkp->seq_post_set_freq) { > + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_post_set_freq, > + clkp->num_seq_post_set_freq); > + if (ret) > + return ret; > + } > + > + if (is_power_on(clkp)) { > + ret = wait_freq_ready(clkp); I should have checked Sashiko before I hit send on my last review. https://sashiko.dev/#/patchset/20260402073957.2742459-1-eleanor.lin%40realtek.com It suggested the following: In the Common Clock Framework, .set_rate executes under the prepare_lock mutex, while .enable and .disable execute under the enable_lock spinlock. Could an interleaved clk_pll_enable() corrupt the hardware state by running its seq_power_on sequence concurrently with these multi-step register updates? There also appears to be a potential race condition later in this function: if (is_power_on(clkp)) { ret = wait_freq_ready(clkp); ... } If .disable() powers off the PLL right before wait_freq_ready() is called, will wait_freq_ready() poll a disabled PLL and erroneously return -ETIMEDOUT? Is a private spinlock needed to serialize these operations? Brian