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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8a596a0a655sm49296476d6.29.2026.04.03.08.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 08:10:55 -0700 (PDT) Date: Fri, 3 Apr 2026 11:10:52 -0400 From: Brian Masney To: Yu-Chun Lin Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, cylee12@realtek.com, afaerber@suse.com, jyanchou@realtek.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-realtek-soc@lists.infradead.org, james.tai@realtek.com, cy.huang@realtek.com, stanley_chang@realtek.com Subject: Re: [PATCH v6 07/10] clk: realtek: Add support for MMC-tuned PLL clocks Message-ID: References: <20260402073957.2742459-1-eleanor.lin@realtek.com> <20260402073957.2742459-8-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260402073957.2742459-8-eleanor.lin@realtek.com> User-Agent: Mutt/2.3.0 (2026-01-25) Hi Yu-Chun, I should have finished going through Sashiko while manually reviewing your patches. On Thu, Apr 02, 2026 at 03:39:54PM +0800, Yu-Chun Lin wrote: > From: Cheng-Yu Lee > > Add clk_pll_mmc_ops for enable/disable, prepare, rate control, and status > operations on MMC PLL clocks. > > Also add clk_pll_mmc_phase_ops to support phase get/set operations. > > Signed-off-by: Cheng-Yu Lee > Co-developed-by: Jyan Chou > Signed-off-by: Jyan Chou > Co-developed-by: Yu-Chun Lin > Signed-off-by: Yu-Chun Lin > --- > +static int clk_pll_mmc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) > +{ > + struct clk_pll_mmc *clkm = to_clk_pll_mmc(hw); > + u32 val = PLL_MMC_SSC_DIV_N_VAL; > + int ret; > + > + ret = regmap_update_bits(clkm->clkr.regmap, > + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, > + PLL_FLAG_INITAL_EMMC_MASK, 0x0 << PLL_FLAG_INITAL_EMMC_SHIFT); > + if (ret) > + return ret; > + > + ret = set_ssc_div_n(clkm, val); > + if (ret) > + return ret; > + > + ret = set_ssc_div_ext_f(clkm, 1517); > + if (ret) > + return ret; > + > + switch (val) { > + case 31 ... 46: > + ret |= set_pi_ibselh(clkm, 3); > + ret |= set_sscpll_rs(clkm, 3); > + ret |= set_sscpll_icp(clkm, 2); Sashiko reports: https://sashiko.dev/#/patchset/20260402073957.2742459-1-eleanor.lin%40realtek.com Is it intended to use bitwise OR to accumulate these return values? Because these hardware operations return standard negative error codes on failure, performing a bitwise OR on multiple negative integers will merge their bit patterns and create a corrupted error code. > + break; > + > + case 20 ... 30: > + ret |= set_pi_ibselh(clkm, 2); > + ret |= set_sscpll_rs(clkm, 3); > + ret |= set_sscpll_icp(clkm, 1); > + break; > + > + case 10 ... 19: > + ret |= set_pi_ibselh(clkm, 1); > + ret |= set_sscpll_rs(clkm, 2); > + ret |= set_sscpll_icp(clkm, 1); > + break; > + > + case 5 ... 9: > + ret |= set_pi_ibselh(clkm, 0); > + ret |= set_sscpll_rs(clkm, 2); > + ret |= set_sscpll_icp(clkm, 0); > + break; > + } > + if (ret) > + return ret; > + > + ret = regmap_update_bits(clkm->clkr.regmap, > + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC3_OFFSET, > + PLL_NCODE_SSC_EMMC_MASK, > + 27 << PLL_NCODE_SSC_EMMC_SHIFT); Sashiko reports: https://sashiko.dev/#/patchset/20260402073957.2742459-1-eleanor.lin%40realtek.com Are the mask and shift values mismatched here? PLL_FLAG_INITAL_EMMC_MASK is defined as BIT(1) (0x02), but PLL_FLAG_INITAL_EMMC_SHIFT is 8. When regmap_update_bits() applies the 0x02 mask to a value shifted by 8, won't it evaluate to 0 and fail to set the intended initialization flag? Brian