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Tue, 07 Apr 2026 12:57:33 -0700 (PDT) X-Received: by 2002:a05:622a:13d4:b0:50d:83a4:2995 with SMTP id d75a77b69052e-50d83a42dbdmr187697771cf.21.1775591853165; Tue, 07 Apr 2026 12:57:33 -0700 (PDT) Received: from redhat.com ([2600:382:772d:3619:ed0:4a9c:acd6:3fc9]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50d4aed181asm164262931cf.0.2026.04.07.12.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Apr 2026 12:57:32 -0700 (PDT) Date: Tue, 7 Apr 2026 15:57:30 -0400 From: Brian Masney To: Marek Vasut Cc: linux-clk@vger.kernel.org, Michael Walle , Conor Dooley , Krzysztof Kozlowski , Michael Turquette , Michael Walle , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 6/6] clk: fsl-sai: Add MCLK generation support Message-ID: References: <20260406215150.176599-1-marex@nabladev.com> <20260406215150.176599-6-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260406215150.176599-6-marex@nabladev.com> User-Agent: Mutt/2.3.0 (2026-01-25) Hi Marek, On Mon, Apr 06, 2026 at 11:49:46PM +0200, Marek Vasut wrote: > The driver currently supports generating BCLK. There are systems which > require generation of MCLK instead. Register new MCLK clock and handle > clock-cells = <1> to differentiate between BCLK and MCLK. In case of a > legacy system with clock-cells = <0>, the driver behaves as before, i.e. > always returns BCLK. > > Note that it is not possible re-use the current SAI audio driver to > generate MCLK and correctly enable and disable the MCLK. > > If SAI (audio driver) is used to control the MCLK enablement, then MCLK > clock is not always enabled, and it is not necessarily enabled when the > codec may need the clock to be enabled. There is also no way for the > codec node to specify phandle to clock provider in DT, because the SAI > (audio driver) is not clock provider. > > If SAI (clock driver) is used to control the MCLK enablement, then MCLK > clock is enabled when the codec needs the clock enabled, because the > codec is the clock consumer and the SAI (clock driver) is the clock > provider, and the codec driver can request the clock to be enabled when > needed. There is also the usual phandle to clock provider in DT, because > the SAI (clock driver) is clock provider. > > Acked-by: Michael Walle > Signed-off-by: Marek Vasut > --- > Cc: Brian Masney > Cc: Conor Dooley > Cc: Krzysztof Kozlowski > Cc: Michael Turquette > Cc: Michael Walle > Cc: Rob Herring > Cc: Stephen Boyd > Cc: devicetree@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > --- > V2: No change > V3: - Rebase on current next, update mail address > - Update commit message according to clarify the difference between > SAI audio and SAI clock driver > - Pick ancient AB from Michael, although this may be outdated > https://patchwork.kernel.org/project/alsa-devel/patch/20241226162234.40141-4-marex@denx.de/ > V4: Use the fsl_sai_clk_register() helper. > --- > drivers/clk/clk-fsl-sai.c | 31 ++++++++++++++++++++++++++++++- > 1 file changed, 30 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c > index 7ec9a4f22735c..386ee5f77a986 100644 > --- a/drivers/clk/clk-fsl-sai.c > +++ b/drivers/clk/clk-fsl-sai.c > @@ -6,6 +6,7 @@ > */ > > #include > +#include This include needs to be moved earlier into the series to keep bisectability. It looks like on patch 2. I'll also comment there. > #include > #include > #include > @@ -15,22 +16,37 @@ > > #define I2S_CSR 0x00 > #define I2S_CR2 0x08 > +#define I2S_MCR 0x100 > #define CSR_BCE_BIT 28 > +#define CSR_TE_BIT 31 > #define CR2_BCD BIT(24) > #define CR2_DIV_SHIFT 0 > #define CR2_DIV_WIDTH 8 > +#define MCR_MOE BIT(30) > > struct fsl_sai_clk { > struct clk_divider bclk_div; > + struct clk_divider mclk_div; > struct clk_gate bclk_gate; > + struct clk_gate mclk_gate; > struct clk_hw *bclk_hw; > + struct clk_hw *mclk_hw; > spinlock_t lock; > }; > > struct fsl_sai_data { > unsigned int offset; /* Register offset */ > + bool have_mclk; /* Have MCLK control */ > }; > > +static struct clk_hw * > +fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data) > +{ > + struct fsl_sai_clk *sai_clk = data; > + > + return clkspec->args[0] ? sai_clk->mclk_hw : sai_clk->bclk_hw; For the case when clock-cells is 0, should this check: clkspec->args_count == 0 || return clkspec->args[0] Brian