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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-907b9772b87sm1051002085a.5.2026.05.11.08.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 08:45:49 -0700 (PDT) Date: Mon, 11 May 2026 11:45:47 -0400 From: Brian Masney To: jian.hu@amlogic.com Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 10/10] clk: amlogic: Add A9 AO clock controller driver Message-ID: References: <20260511-b4-a9_clk-v1-0-41cb4071b7c9@amlogic.com> <20260511-b4-a9_clk-v1-10-41cb4071b7c9@amlogic.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260511-b4-a9_clk-v1-10-41cb4071b7c9@amlogic.com> User-Agent: Mutt/2.3.1 (2026-03-20) Hi Jian, On Mon, May 11, 2026 at 08:47:32PM +0800, Jian Hu via B4 Relay wrote: > From: Jian Hu > > Add the Always-on clock controller driver for the Amlogic A9 SoC family. > > Signed-off-by: Jian Hu I'll only flag new things that I spot here that weren't mentioned in the other patches I reviewed in this series. > --- > drivers/clk/meson/Makefile | 2 +- > drivers/clk/meson/a9-aoclk.c | 494 +++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 495 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile > index 2b5b67b14efc..91af609ce815 100644 > --- a/drivers/clk/meson/Makefile > +++ b/drivers/clk/meson/Makefile > @@ -20,7 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o > obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o > obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o > obj-$(CONFIG_COMMON_CLK_A9_PLL) += a9-pll.o > -obj-$(CONFIG_COMMON_CLK_A9_PERIPHERALS) += a9-peripherals.o > +obj-$(CONFIG_COMMON_CLK_A9_PERIPHERALS) += a9-peripherals.o a9-aoclk.o > obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o > obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o > obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o > diff --git a/drivers/clk/meson/a9-aoclk.c b/drivers/clk/meson/a9-aoclk.c > new file mode 100644 > index 000000000000..3c42eaf585d2 > --- /dev/null > +++ b/drivers/clk/meson/a9-aoclk.c > @@ -0,0 +1,494 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) > +/* > + * Copyright (C) 2026 Amlogic, Inc. All rights reserved > + */ > + > +#include > +#include > +#include > +#include "clk-regmap.h" > +#include "clk-dualdiv.h" > +#include "meson-clkc-utils.h" > + > +#define AO_OSCIN_CTRL 0x00 > +#define AO_SYS_CLK0 0x04 > +#define AO_PWM_CLK_A_CTRL 0x1c > +#define AO_PWM_CLK_B_CTRL 0x20 > +#define AO_PWM_CLK_C_CTRL 0x24 > +#define AO_PWM_CLK_D_CTRL 0x28 > +#define AO_PWM_CLK_E_CTRL 0x2c > +#define AO_PWM_CLK_F_CTRL 0x30 > +#define AO_PWM_CLK_G_CTRL 0x34 > +#define AO_CEC_CTRL0 0x38 > +#define AO_CEC_CTRL1 0x3c > +#define AO_RTC_BY_OSCIN_CTRL0 0x50 > +#define AO_RTC_BY_OSCIN_CTRL1 0x54 > + > +#define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ > + MESON_COMP_SEL(a9_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) > + > +#define A9_COMP_DIV(_name, _reg, _shift, _width) \ > + MESON_COMP_DIV(a9_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) > + > +#define A9_COMP_GATE(_name, _reg, _bit) \ > + MESON_COMP_GATE(a9_, _name, _reg, _bit, CLK_SET_RATE_PARENT) > + > +static struct clk_regmap a9_ao_xtal_in = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = AO_OSCIN_CTRL, > + .bit_idx = 3, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "ao_xtal_in", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + /* > + * It may be ao_sys's parent clock, its child clocks mark > + * CLK_IS_CRITICAL, So mark CLK_IS_CRITICAL for it. > + */ > + .flags = CLK_IS_CRITICAL, > + }, > +}; > + > +static struct clk_regmap a9_ao_xtal = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = AO_OSCIN_CTRL, > + .mask = 0x1, > + .shift = 0, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "ao_xtal", > + .ops = &clk_regmap_mux_ops, > + /* ext_32k is from external PAD, do not automatically reparent */ > + .parent_data = (const struct clk_parent_data []) { > + { .hw = &a9_ao_xtal_in.hw }, > + { .fw_name = "ext_32k", }, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_NO_REPARENT, > + }, > +}; > + > +static struct clk_regmap a9_ao_sys = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = AO_OSCIN_CTRL, > + .mask = 0x1, > + .shift = 1, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "ao_sys", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .hw = &a9_ao_xtal.hw }, > + { .fw_name = "sys", }, > + }, > + .num_parents = 2, > + .flags = CLK_SET_PARENT_GATE, > + }, > +}; > + > +static const struct clk_parent_data a9_ao_pclk_parents = { .hw = &a9_ao_sys.hw }; > + > +#define A9_AO_PCLK(_name, _bit, _flags) \ > + MESON_PCLK(a9_ao_sys_##_name, AO_SYS_CLK0, _bit, \ > + &a9_ao_pclk_parents, _flags) > + > +/* > + * A9 integrates a low-power microprocessor (Always-on CPU: AOCPU). Some AO sys > + * clocks control the AOCPU modules. Mark the AOCPU-related clocks with > + * CLK_IS_CRITICAL to avoid them being disabled and impacting AOCPU functionality. > + * AOCPU-related clocks list: > + * - clktree > + * - rst_ctrl > + * - pad > + * - irq > + * - pwrctrl > + * - aocpu > + * - sram > + */ > +static A9_AO_PCLK(i2c3, 0, 0); > +static A9_AO_PCLK(rtc_reg, 1, 0); > +static A9_AO_PCLK(clktree, 2, CLK_IS_CRITICAL); > +static A9_AO_PCLK(rst_ctrl, 3, CLK_IS_CRITICAL); > +static A9_AO_PCLK(pad, 4, CLK_IS_CRITICAL); > +static A9_AO_PCLK(rtc_dig, 5, 0); > +static A9_AO_PCLK(irq, 6, CLK_IS_CRITICAL); > +static A9_AO_PCLK(pwrctrl, 7, CLK_IS_CRITICAL); > +static A9_AO_PCLK(pwm_a, 8, 0); > +static A9_AO_PCLK(pwm_b, 9, 0); > +static A9_AO_PCLK(pwm_c, 10, 0); > +static A9_AO_PCLK(pwm_d, 11, 0); > +static A9_AO_PCLK(pwm_e, 12, 0); > +static A9_AO_PCLK(pwm_f, 13, 0); > +static A9_AO_PCLK(pwm_g, 14, 0); > +static A9_AO_PCLK(i2c_a, 15, 0); > +static A9_AO_PCLK(i2c_b, 16, 0); > +static A9_AO_PCLK(i2c_c, 17, 0); > +static A9_AO_PCLK(i2c_d, 18, 0); > +static A9_AO_PCLK(sed, 19, 0); > +static A9_AO_PCLK(ir_ctrl, 20, 0); > +static A9_AO_PCLK(uart_b, 21, 0); > +static A9_AO_PCLK(uart_c, 22, 0); > +static A9_AO_PCLK(uart_d, 23, 0); > +static A9_AO_PCLK(uart_e, 24, 0); > +static A9_AO_PCLK(spisg_0, 25, 0); > +static A9_AO_PCLK(rtc_secure, 26, 0); > +static A9_AO_PCLK(cec, 27, 0); > +static A9_AO_PCLK(aocpu, 28, CLK_IS_CRITICAL); > +static A9_AO_PCLK(sram, 29, CLK_IS_CRITICAL); > +static A9_AO_PCLK(spisg_1, 30, 0); > +static A9_AO_PCLK(spisg_2, 31, 0); > + > +static const struct clk_parent_data a9_ao_pwm_parents[] = { > + { .hw = &a9_ao_xtal.hw }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", } > +}; > + > +static A9_COMP_SEL(ao_pwm_a, AO_PWM_CLK_A_CTRL, 9, 0x7, a9_ao_pwm_parents); > +static A9_COMP_DIV(ao_pwm_a, AO_PWM_CLK_A_CTRL, 0, 8); > +static A9_COMP_GATE(ao_pwm_a, AO_PWM_CLK_A_CTRL, 8); > + > +static A9_COMP_SEL(ao_pwm_b, AO_PWM_CLK_B_CTRL, 9, 0x7, a9_ao_pwm_parents); > +static A9_COMP_DIV(ao_pwm_b, AO_PWM_CLK_B_CTRL, 0, 8); > +static A9_COMP_GATE(ao_pwm_b, AO_PWM_CLK_A_CTRL, 8); Should this be AO_PWM_CLK_B_CTRL ? > + > +static A9_COMP_SEL(ao_pwm_c, AO_PWM_CLK_C_CTRL, 9, 0x7, a9_ao_pwm_parents); > +static A9_COMP_DIV(ao_pwm_c, AO_PWM_CLK_C_CTRL, 0, 8); > +static A9_COMP_GATE(ao_pwm_c, AO_PWM_CLK_C_CTRL, 8); > + > +static A9_COMP_SEL(ao_pwm_d, AO_PWM_CLK_D_CTRL, 9, 0x7, a9_ao_pwm_parents); > +static A9_COMP_DIV(ao_pwm_d, AO_PWM_CLK_D_CTRL, 0, 8); > +static A9_COMP_GATE(ao_pwm_d, AO_PWM_CLK_D_CTRL, 8); > + > +static A9_COMP_SEL(ao_pwm_e, AO_PWM_CLK_E_CTRL, 9, 0x7, a9_ao_pwm_parents); > +static A9_COMP_DIV(ao_pwm_e, AO_PWM_CLK_E_CTRL, 0, 8); > +static A9_COMP_GATE(ao_pwm_e, AO_PWM_CLK_E_CTRL, 8); > + > +static A9_COMP_SEL(ao_pwm_f, AO_PWM_CLK_F_CTRL, 9, 0x7, a9_ao_pwm_parents); > +static A9_COMP_DIV(ao_pwm_f, AO_PWM_CLK_F_CTRL, 0, 8); > +static A9_COMP_GATE(ao_pwm_f, AO_PWM_CLK_F_CTRL, 8); > + > +static A9_COMP_SEL(ao_pwm_g, AO_PWM_CLK_G_CTRL, 9, 0x7, a9_ao_pwm_parents); > +static A9_COMP_DIV(ao_pwm_g, AO_PWM_CLK_G_CTRL, 0, 8); > +static A9_COMP_GATE(ao_pwm_g, AO_PWM_CLK_G_CTRL, 8); > + > +static struct clk_regmap a9_ao_rtc_dualdiv_in = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = AO_RTC_BY_OSCIN_CTRL0, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "ao_rtc_duandiv_in", s/duandiv/dualdiv/ ? Brian