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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-914f881d91csm270637885a.44.2026.05.26.11.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2026 11:06:55 -0700 (PDT) Date: Tue, 26 May 2026 14:06:53 -0400 From: Brian Masney To: Joey Lu Cc: mturquette@baylibre.com, sboyd@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/3] clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc Message-ID: References: <20260521014220.77955-1-a0987203069@gmail.com> <20260521014220.77955-3-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260521014220.77955-3-a0987203069@gmail.com> User-Agent: Mutt/2.3.1 (2026-03-20) On Thu, May 21, 2026 at 09:42:19AM +0800, Joey Lu wrote: > PLL_CTL1_FRAC was defined as GENMASK(31, 24), covering only 8 bits. > The hardware fractional field occupies bits [31:8] (24 bits), so the > mask must be GENMASK(31, 8). > > The previous fractional-mode calculation used FIELD_MAX(PLL_CTL1_FRAC) > as the denominator to obtain 2 decimal places. With the corrected 24-bit > mask the old divisor is wrong; replace the arithmetic with a proper > 24-bit fixed-point rounding to 3 decimal places using the kernel's > DIV_ROUND_CLOSEST_ULL helper: > > n_frac = n * 1000 + DIV_ROUND_CLOSEST_ULL(x * 1000, 1 << 24) > > Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") > Signed-off-by: Joey Lu Reviewed-by: Brian Masney