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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-517fb61eaf4sm120318231cf.4.2026.06.15.15.01.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 15:01:36 -0700 (PDT) Date: Mon, 15 Jun 2026 18:01:34 -0400 From: Brian Masney To: V.Yurkov.EXT@bruker.com Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Vyacheslav Yurkov Subject: Re: [PATCH v3 1/2] dt-bindings: Add GPIO-locked fixed clock Message-ID: References: <20260603-feature-clock-guard-v3-0-01cca0aa04a5@bruker.com> <20260603-feature-clock-guard-v3-1-01cca0aa04a5@bruker.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260603-feature-clock-guard-v3-1-01cca0aa04a5@bruker.com> User-Agent: Mutt/2.3.1 (2026-03-20) Hi Vyacheslav, On Wed, Jun 03, 2026 at 11:16:42AM +0000, Vyacheslav Yurkov via B4 Relay wrote: > From: Vyacheslav Yurkov > > Some hardware designs provide fixed-frequency clocks generated outside > software control, such as by FPGA-resident PLLs. While the clock rate is > fixed, a separate GPIO signal indicates whether the clock source is > locked and producing a valid output. > > Describe a GPIO-locked fixed clock provider that exposes a fixed-rate > clock whose availability depends on one or more GPIO lock-status > signals. > > Signed-off-by: Vyacheslav Yurkov > Signed-off-by: Vyacheslav Yurkov > --- > .../bindings/clock/gpio-locked-fixed-clock.yaml | 70 ++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/gpio-locked-fixed-clock.yaml b/Documentation/devicetree/bindings/clock/gpio-locked-fixed-clock.yaml > new file mode 100644 > index 000000000000..9106b800b673 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/gpio-locked-fixed-clock.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/gpio-locked-fixed-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: GPIO Locked Fixed Clock > + > +maintainers: > + - Vyacheslav Yurkov > + > +description: | > + Provides a clock output whose availability depends on a set of > + prerequisite conditions. These conditions include the presence of > + one or more parent clocks and the asserted state of one or more > + GPIO lock indicators. An example of such clocks is FPGA clock that > + are outside CPU control, with the lock status exposed through GPIO > + signal. > + > + The output clock is considered available only when all configured > + prerequisites are satisfied. I'm stepping outside my usual review of just the clk drivers. Krzysztof in v1 and v2 asked for more detailed hardware explanation. This feels to me like this is a policy that says to not use these clocks until the GPIO says they are ready. My gut feeling is that details like this should live in a clk driver instead of a dt-binding. Alternatively, if this is generic enough, then could Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml be extended? Brian > + > +properties: > + compatible: > + const: gpio-locked-fixed-clock > + > + "#clock-cells": > + const: 0 > + > + clocks: > + description: Input clocks whose validity is monitored by this provider. > + > + clock-output-names: > + description: Names of the clock provided by this controller. > + maxItems: 1 > + > + locked-gpios: > + description: | > + GPIOs to check the lock state. > + minItems: 1 > + maxItems: 32 > + > +required: > + - compatible > + - "#clock-cells" > + > +anyOf: > + - required: > + - clocks > + - required: > + - locked-gpios > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + clk_gpio_locked: gpio-locked-fixed-clock { > + compatible = "gpio-locked-fixed-clock"; > + #clock-cells = <0>; > + > + clocks = <&clk0 0>, <&pll 0>; > + > + locked-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>, > + <&gpio0 5 GPIO_ACTIVE_HIGH>, > + <&gpio1 2 GPIO_ACTIVE_LOW>; > + > + clock-output-names = "clkout0"; > + }; > > -- > 2.34.1 > >