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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c6f4993a1sm185163eec.17.2026.06.23.19.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2026 19:52:46 -0700 (PDT) Date: Wed, 24 Jun 2026 10:52:39 +0800 From: Shawn Guo To: Taniya Das Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 5/6] dt-bindings: clock: qcom: Document Nord GPU clock controllers Message-ID: References: <20260623-nords_mm_v1-v1-0-860c84539804@oss.qualcomm.com> <20260623-nords_mm_v1-v1-5-860c84539804@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260623-nords_mm_v1-v1-5-860c84539804@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI0MDAyMiBTYWx0ZWRfX/xEnv7YFmb8R AgLaYfF+XjobyYA3eVUlF3vZQAF8LzAlaSuLIIhNavYU6kSrSH8uzOWpV1JAG627skP+EP2Yg+w BPHyKi97cSnhyREPQJ+mLym+egSD3wCbdm5tBtkUHYrUy5k7tWC8gedeX/T/RfkD29SlLZN+vk7 l3G8hVv/hAcwdoZMhmHkSJugzOHjy6pPV+yxpyXtvtwOtxROPzdii6BE4Re/wvhpz9R3FSyBMY4 QkXdWQ2cX+bH0d57mG/CUHRqVzrui9RDIQGgGg4rXZuo3+W5B2cYNks/UvfD2FPAbDYnVJymWsQ L6RCRcoe9YWtdr4sQGuga3hd0CXaCz6zA9DT+rYHvzq98d5jErOp6PtSbaaDFtMI7ykisewaepD Pxv3xXBb3+A527/pOZ1XgdwTPQPWwO6XT8DG4GhLsHKS+UIQfOLdWEKza72cILAC5/Ji6ZY42Mx fCCn+FFO/b+sfLay+gQ== X-Proofpoint-ORIG-GUID: 8mC1u-UZuTdCz5fCF3qt-SBCdTOLYl2w X-Proofpoint-GUID: 8mC1u-UZuTdCz5fCF3qt-SBCdTOLYl2w X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI0MDAyMiBTYWx0ZWRfX7PfaUcWtdtWX XEUjOsD5kxFfLKrLXvTVcXzUh8wcMLKbV1B8G3j4FLAcwKTXZA7kMru+pcieWzcjt8h284DJbEV kZSWJuN4I44quNvDfOZXYR378xOxzPU= X-Authority-Analysis: v=2.4 cv=JbaMa0KV c=1 sm=1 tr=0 ts=6a3b4680 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=1IcVdnUytOkCmWWg2wsA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-24_01,2026-06-23_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 suspectscore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606240022 On Tue, Jun 23, 2026 at 04:24:08PM +0530, Taniya Das wrote: > Add Device Tree binding documentation for the GPU clock controllers > on the Qualcomm Nord platform. > > The platform includes two GPU clock controller instances, GPUCC and > GPUCC2. Document the compatible strings for both controllers. > > Signed-off-by: Taniya Das > --- > .../bindings/clock/qcom,sm8450-gpucc.yaml | 3 ++ > include/dt-bindings/clock/qcom,nord-gpucc.h | 51 ++++++++++++++++++++++ > 2 files changed, 54 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml > index fdbdf605ee695637512ce4f98c9b6fcfacb9154f..ba85692240e07a4ed8e69c6b61847c5601b32fa0 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml > @@ -18,6 +18,7 @@ description: | > include/dt-bindings/clock/qcom,glymur-gpucc.h > include/dt-bindings/clock/qcom,kaanapali-gpucc.h > include/dt-bindings/clock/qcom,milos-gpucc.h > + include/dt-bindings/clock/qcom,nord-gpucc.h > include/dt-bindings/clock/qcom,sar2130p-gpucc.h > include/dt-bindings/clock/qcom,sm4450-gpucc.h > include/dt-bindings/clock/qcom,sm8450-gpucc.h > @@ -33,6 +34,8 @@ properties: > - qcom,glymur-gpucc > - qcom,kaanapali-gpucc > - qcom,milos-gpucc > + - qcom,nord-gpu2cc > + - qcom,nord-gpucc I see inconsistency in naming between dispcc0/dispcc1 and gpucc/gpu2cc. Shawn