From: Brian Masney <bmasney@redhat.com>
To: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
"Akari Tsuyukusa" <akkun11.open@gmail.com>,
"Chen Ni" <nichen@iscas.ac.cn>,
"Chen-Yu Tsai" <wenst@chromium.org>,
"Christian Marangi" <ansuelsmth@gmail.com>,
"Colin Foster" <colin.foster@in-advantage.com>,
"Dan Carpenter" <error27@gmail.com>,
"Dmitry Osipenko" <digetx@gmail.com>,
"Guangshuo Li" <lgs201920130244@gmail.com>,
"Herve Codina" <herve.codina@bootlin.com>,
"Jerome Brunet" <jbrunet@baylibre.com>,
"Jia Wang" <wangjia@ultrarisc.com>,
"Joakim Zhang" <joakim.zhang@cixtech.com>,
"Kostas Damaskinakis" <kostas.damaskinakis@gmail.com>,
"longlong yan" <yanlonglong@kylinos.cn>,
"Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>,
"Myeonghun Pak" <mhun512@gmail.com>,
"Pavel Löbl" <pavel@loebl.cz>,
"Pengpeng Hou" <pengpeng@iscas.ac.cn>,
"Rosen Penev" <rosenp@gmail.com>,
"Ryan Chen" <ryan_chen@aspeedtech.com>,
"Sang-Heon Jeon" <ekffu200098@gmail.com>,
"Shubhrajyoti Datta" <shubhrajyoti.datta@amd.com>,
"Suraj Gupta" <suraj.gupta2@amd.com>,
"Svyatoslav Ryhel" <clamor95@gmail.com>,
"Wolfram Sang" <wsa+renesas@sang-engineering.com>,
"Uwe Kleine-König" <u.kleine-koenig@baylibre.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>
Subject: [GIT PULL] clk: Clock driver updates for v7.3 (round two)
Date: Tue, 28 Jul 2026 12:39:18 -0400 [thread overview]
Message-ID: <amjbNiVjm5HkPRu9@redhat.com> (raw)
Hi Stephen and Michael,
Here's some changes that were posted since June 29th that I feel are ready to
be picked up. These are changes where a clk submaintainer typically won't send
the changes in via a separate pull.
Note that I have a separate outstanding pull for some changes posted during
the last merge window that I feel is also ready for inclusion.
https://lore.kernel.org/linux-clk/akLzCVzbMbUsgDda@redhat.com/
There is a minor conflict in drivers/clk/clk-si544.c between these two pulls.
You'll need to add the .name and .driver_data name initializers like the
following based on the work from Uwe Kleine-König:
- { "si544a", (kernel_ulong_t)&clk_si544a_info },
+ { .name = "si544a", .driver_data = (kernel_ulong_t)&clk_si544a_info },
With the conflict resolved, I verified that both merges can go in together, or
individually.
The following changes since commit dc59e4fea9d83f03bad6bddf3fa2e52491777482:
Linux 7.2-rc1 (2026-06-28 12:01:31 -0700)
are available in the Git repository at:
https://github.com/masneyb/linux tags/clk-misc-round-two-for-v7.3
for you to fetch changes up to cf561283254dd9f55805800237e6f82f08d91497:
clk: tegra: set up proper EMC clock implementation for Tegra114 (2026-07-28 11:31:34 -0400)
----------------------------------------------------------------
clk: Clock driver updates for v7.3 (round two)
- New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS),
UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree
bindings. Si549 support was added to the existing si544 driver.
- New clock and reset support for the Aspeed AST2700 PECI controller and Airoha
EN7523 PCIe PERSTOUT reset lines.
- The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to
the existing optional variant, and exports
devm_clk_hw_register_composite_pdata() for modular drivers.
- Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1
support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL
charge pump/lock parameter programming during dynamic reconfiguration.
- Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in
the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted
gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on
registration failure, a prepare reference leak in the palmas driver,
unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in
pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a
clocking-wizard clock difference detection bug.
- Various cleanups across tegra, st, and mvebu providers to stop misusing the
consumer clock API, along with other minor fixes and improvements.
Signed-off-by: Brian Masney <bmasney@redhat.com>
----------------------------------------------------------------
Akari Tsuyukusa (1):
clk: mediatek: mt8135: Fix inverted gate control for devapc_ck
Chen Ni (2):
clk: mmp: pxa1908-apbc: Remove unneeded semicolon
clk: mmp: pxa1908-apbcp: Remove unneeded semicolon
Chen-Yu Tsai (2):
dt-bindings: clock: mediatek: Add mt8173 mfgtop
clk: mediatek: Add mt8173-mfgtop driver
Christian Marangi (3):
clk: en7523: reset PCIE HB on init for AN7581
dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT
clk: en7523: add support for dedicated PCIe PERSTOUT reset
Colin Foster (3):
clk: clocking-wizard: fix clock difference detection
clk: clocking-wizard: optimize clock search
clk: clocking-wizard: remove 20kHz restriction
Dan Carpenter (1):
clk: document that clk_get_parent() returns NULL
Dmitry Osipenko (1):
clk: tegra: support 48MHz clock for pll_p_out1
Guangshuo Li (1):
clk: tegra: tegra124-emc: put EMC node on register failure
Herve Codina (1):
clk: lan966x: Add MCHP_LAN966X_PCI dependency
Jerome Brunet (3):
clk: mvebu: clean-up simple provider misuse of the consumer API
clk: st: clean-up simple provider misuse of the consumer API
clk: tegra: clean-up simple provider misuse of the consumer API
Jia Wang (3):
clk: composite: Export devm composite pdata helper
dt-bindings: clock: ultrarisc: Add DP1000 Clock Controller
clk: ultrarisc: Add DP1000 clock driver
Joakim Zhang (4):
dt-bindings: soc: cix: add sky1 audss cru controller
clk: cix: add sky1 audss clock controller
reset: cix: add sky1 audss auxiliary reset driver
arm64: dts: cix: sky1: add audss cru
Kostas Damaskinakis (1):
clk: eswin: Zero-initialize stack-allocated clk_init_data
Louis-Alexis Eyraud (1):
clk: mediatek: pllfh: Fix IO remapping leak in register_pllfhs error path
Myeonghun Pak (3):
clk: mediatek: mt6735: Unregister PLLs on probe failure
clk: palmas: Manage external-control prepare with devm
clk: palmas: Use devm_of_clk_add_hw_provider()
Pavel Löbl (2):
dt-bindings: clock: si544: add si549 compatible
clk: si544: add support for si549
Pengpeng Hou (2):
clk: mediatek: mt6735-vdecsys: add missing MODULE_DEVICE_TABLE()
clk: mediatek: mt6735-vencsys: add missing MODULE_DEVICE_TABLE()
Rosen Penev (3):
clk: stm32: add missing bitfield.h header
clk: stm32: allow STM32MP COMPILE_TEST builds
clk: hisilicon: hi3660-stub: use devm_platform_ioremap_resource
Ryan Chen (2):
dt-bindings: clock: ast2700: add PECI clock
clk: aspeed: add AST2700 PECI clock
Sang-Heon Jeon (1):
clk: remove conditional return with no effect
Shubhrajyoti Datta (1):
clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig
Suraj Gupta (1):
clk: Add devm_clk_bulk_get_enable()
Svyatoslav Ryhel (1):
clk: tegra: set up proper EMC clock implementation for Tegra114
Wolfram Sang (1):
clk: mediatek: remove unneeded 'fast_io' parameter in regmap_config
longlong yan (1):
clk/x86: pmc_atom: add kasprintf return value check
.../bindings/clock/mediatek,mt8173-mfgtop.yaml | 70 ++
.../devicetree/bindings/clock/silabs,si544.yaml | 10 +-
.../bindings/clock/ultrarisc,dp1000-clk.yaml | 60 +
.../bindings/soc/cix/cix,sky1-audss-cru.yaml | 92 ++
Documentation/driver-api/driver-model/devres.rst | 1 +
MAINTAINERS | 8 +
arch/arm64/boot/dts/cix/sky1.dtsi | 18 +
drivers/clk/Kconfig | 10 +-
drivers/clk/Makefile | 4 +-
drivers/clk/aspeed/clk-ast2700.c | 10 +
drivers/clk/cix/Kconfig | 16 +
drivers/clk/cix/Makefile | 3 +
drivers/clk/cix/clk-sky1-audss.c | 1206 ++++++++++++++++++++
drivers/clk/clk-composite.c | 1 +
drivers/clk/clk-cs2000-cp.c | 6 +-
drivers/clk/clk-devres.c | 7 +
drivers/clk/clk-en7523.c | 43 +-
drivers/clk/clk-lmk04832.c | 12 +-
drivers/clk/clk-palmas.c | 24 +-
drivers/clk/clk-si544.c | 82 +-
drivers/clk/eswin/clk.c | 4 +-
drivers/clk/hisilicon/clk-hi3660-stub.c | 10 +-
drivers/clk/mediatek/Kconfig | 10 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 5 +-
drivers/clk/mediatek/clk-mt6735-vdecsys.c | 1 +
drivers/clk/mediatek/clk-mt6735-vencsys.c | 1 +
drivers/clk/mediatek/clk-mt8135.c | 5 +-
drivers/clk/mediatek/clk-mt8173-mfgtop.c | 242 ++++
drivers/clk/mediatek/clk-mt8196-vlpckgen.c | 1 -
drivers/clk/mediatek/clk-pllfh.c | 98 +-
drivers/clk/mmp/clk-pxa1908-apbc.c | 2 +-
drivers/clk/mmp/clk-pxa1908-apbcp.c | 2 +-
drivers/clk/mvebu/clk-cpu.c | 2 +-
drivers/clk/st/clkgen-pll.c | 20 +-
drivers/clk/stm32/clk-stm32mp21.c | 1 +
drivers/clk/stm32/clk-stm32mp25.c | 1 +
drivers/clk/tegra/clk-pll.c | 1 +
drivers/clk/tegra/clk-tegra114.c | 39 +-
drivers/clk/tegra/clk-tegra124-emc.c | 1 +
drivers/clk/tegra/clk-tegra210.c | 2 +-
drivers/clk/ultrarisc/Kconfig | 18 +
drivers/clk/ultrarisc/Makefile | 4 +
drivers/clk/ultrarisc/clk-dp1000.c | 154 +++
drivers/clk/ultrarisc/clk-ultrarisc.c | 399 +++++++
drivers/clk/ultrarisc/clk-ultrarisc.h | 71 ++
drivers/clk/x86/clk-pmc-atom.c | 3 +
drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 142 ++-
drivers/reset/Kconfig | 13 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-sky1-audss.c | 127 +++
include/dt-bindings/clock/aspeed,ast2700-scu.h | 2 +
include/dt-bindings/clock/cix,sky1-audss-cru.h | 60 +
include/dt-bindings/clock/mt8173-clk.h | 7 +
include/dt-bindings/clock/ultrarisc,dp1000-clk.h | 27 +
include/dt-bindings/reset/airoha,en7581-reset.h | 4 +
include/dt-bindings/reset/cix,sky1-audss-cru.h | 25 +
include/linux/clk.h | 27 +-
58 files changed, 3065 insertions(+), 151 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml
create mode 100644 Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml
create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml
create mode 100644 drivers/clk/cix/Kconfig
create mode 100644 drivers/clk/cix/Makefile
create mode 100644 drivers/clk/cix/clk-sky1-audss.c
create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
create mode 100644 drivers/clk/ultrarisc/Kconfig
create mode 100644 drivers/clk/ultrarisc/Makefile
create mode 100644 drivers/clk/ultrarisc/clk-dp1000.c
create mode 100644 drivers/clk/ultrarisc/clk-ultrarisc.c
create mode 100644 drivers/clk/ultrarisc/clk-ultrarisc.h
create mode 100644 drivers/reset/reset-sky1-audss.c
create mode 100644 include/dt-bindings/clock/cix,sky1-audss-cru.h
create mode 100644 include/dt-bindings/clock/ultrarisc,dp1000-clk.h
create mode 100644 include/dt-bindings/reset/cix,sky1-audss-cru.h
reply other threads:[~2026-07-28 16:39 UTC|newest]
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