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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: "Arnd Bergmann" <arnd@arndb.de>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Linus Walleij" <linusw@kernel.org>,
	"Bartosz Golaszewski" <brgl@kernel.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>, "Long Zhao" <zl020895@163.com>,
	"Lee Jones" <lee@kernel.org>,
	mfd@lists.linux.dev, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
	linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 10/13] pinctrl: ambarella: add CV75 pin controller
Date: Fri, 4 Sep 2026 16:29:52 +0300	[thread overview]
Message-ID: <aprH0EAx6PlQuoxq@ashevche-desk.local> (raw)
In-Reply-To: <20260904-cv75-v5-v6-10-e918514cb3b1@ambarella.com>

On Fri, Sep 04, 2026 at 02:38:17PM +0800, Long Zhao via B4 Relay wrote:

> Add an Ambarella pinmux-only pinctrl driver with CV75 function/group
> tables. GPIO is handled by the PL061 driver.

...

> +#include <linux/kernel.h>

Absolutely no. Follow IWYU principle in all your patches.

...

> +#define CV75_GROUP(_name)						\
> +	{								\
> +		.name = #_name,						\
> +		.pinmux = cv75_##_name##_pinmux,				\
> +		.num_pins = ARRAY_SIZE(cv75_##_name##_pinmux),		\
> +	}
> +
> +#define CV75_FUNCTION(_name)						\
> +	{								\
> +		.name = #_name,						\
> +		.groups = cv75_##_name##_groups,				\
> +		.num_groups = ARRAY_SIZE(cv75_##_name##_groups),		\
> +	}

Don't we have respective macros in linux/pinctrl/pinctrl.h

...

> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/bitmap.h>
> +#include <linux/io.h>

> +#include <linux/of.h>
> +#include <linux/of_device.h>



> +#include <linux/slab.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include <linux/pinctrl/pinconf.h>
> +#include <linux/pinctrl/pinconf-generic.h>
> +#include <linux/seq_file.h>

Make it ordered, group linux/pinctrl/ separately after generic linux/*.h

> +#include "pinconf.h"
> +#include "pinctrl-ambarella.h"

...

> +struct amb_pinctrl_soc_data {
> +	struct device			*dev;
> +	const struct amb_pinctrl_data	*data;
> +	void __iomem			*iomux_base;
> +	struct regmap			*ds_regmap;
> +	struct regmap			*pull_regmap;
> +	unsigned int			npins;
> +	unsigned long			used[BITS_TO_LONGS(AMBA_MAX_PINS)];
> +	raw_spinlock_t lock;
> +
> +	struct pinctrl_dev		*pctl;

> +	const struct ambpin_function	*functions;
> +	unsigned int			nr_functions;
> +	struct ambpin_group		*groups;
> +	unsigned int			nr_groups;

Check what linux/pinctrl/pinctrl.h and drivers/pinctrl/core.h provide.

> +};

...

> +#if IS_ENABLED(CONFIG_DEBUG_FS)
> +static void amb_pin_dbg_show(struct pinctrl_dev *pctldev,
> +			     struct seq_file *s, unsigned int pin)
> +{
> +	seq_printf(s, " %s", pinctrl_dev_get_devname(pctldev));
> +}
> +#endif

Does this bring any new information?

...

> +/* check if the selector is a valid pin function selector */
> +static int amb_pinmux_request(struct pinctrl_dev *pctldev, unsigned int pin)
> +{
> +	struct amb_pinctrl_soc_data *soc = pinctrl_dev_get_drvdata(pctldev);
> +
> +	if (test_and_set_bit(pin, soc->used))
> +		return -EBUSY;
> +
> +	return 0;
> +}
> +
> +/* check if the selector is a valid pin function selector */
> +static int amb_pinmux_free(struct pinctrl_dev *pctldev, unsigned int pin)
> +{
> +	struct amb_pinctrl_soc_data *soc = pinctrl_dev_get_drvdata(pctldev);
> +
> +	clear_bit(pin, soc->used);
> +
> +	return 0;
> +}

Why? Isn't internal pinctrl tracking is not enough?

...

> +static void amb_pinmux_set_altfunc(struct amb_pinctrl_soc_data *soc,
> +				   u32 bank, u32 offset, u32 altfunc)
> +{
> +	u32 i, data;
> +
> +	if (!amb_iomux_accessible(soc))
> +		return;
> +
> +	for (i = 0; i < 3; i++) {

	for (unsigned int i...

> +		data = readl_relaxed(soc->iomux_base + IOMUX_OFFSET(bank, i));
> +		data &= ~BIT(offset);
> +		data |= ((altfunc >> i) & 1U) << offset;
> +		writel_relaxed(data, soc->iomux_base + IOMUX_OFFSET(bank, i));
> +	}
> +}

...

> +static int amb_drive_strength_to_reg(struct amb_pinctrl_soc_data *soc,
> +				     u32 strength)
> +{
> +	if (soc->data->have_ds2) {
> +		switch (strength) {
> +		case 3:
> +			return 0;
> +		case 4:
> +		case 5:
> +			return 1;
> +		case 6:
> +			return 2;
> +		case 7:
> +		case 8:
> +			return 3;
> +		case 9:
> +			return 4;
> +		case 12:
> +			return 5;
> +		default:
> +			return -EINVAL;
> +		}
> +	}
> +
> +	switch (strength) {
> +	case 2:
> +		return 0;
> +	case 4:
> +		return 1;
> +	case 8:
> +		return 2;
> +	case 12:
> +		return 3;
> +	default:
> +		return -EINVAL;
> +	}
> +}

I would look better in three functions

static int amb_drive_strength_to_reg(struct amb_pinctrl_soc_data *soc,
				     u32 strength)
{
	if (soc->data->have_ds2)
		return amb_drive_strength_to_reg_ds2(soc, strength);

	return amb_drive_strength_to_reg_ds1(soc, strength);

}

> +static int amb_reg_to_drive_strength(struct amb_pinctrl_soc_data *soc, u32 ds)
> +{
> +	static const int ds2_ma[] = { 3, 4, 6, 8, 9, 12 };
> +	static const int ds_ma[] = { 2, 4, 8, 12 };

You have switch cases that use the same arrays, use them for both.

> +	if (soc->data->have_ds2) {
> +		if (ds >= ARRAY_SIZE(ds2_ma))
> +			return -EINVAL;
> +
> +		return ds2_ma[ds];
> +	}
> +
> +	if (ds >= ARRAY_SIZE(ds_ma))
> +		return -EINVAL;
> +
> +	return ds_ma[ds];
> +}

...

I stopped here, this driver is quite far from the modern pin control standards,
please look around, you find a lot of new drivers there, that are written in
more-or-less compact ways, using better APIs and approaches.

When creating a driver, use also helper tools, like `pahole`,
scripts/bloat-o-meter, et cetera. Compile with `make W=1 C=1 ...`
using both compilers (GCC and clang).

...

> +static const struct of_device_id amb_pinctrl_dt_match[] = {
> +	{
> +		.compatible = "ambarella,cv75-pinctrl",
> +		.data = &ambarella_cv75_pinctrl_data,
> +	},
> +	{},

No trailing comma for the terminator entry.

> +};

...

> +static struct platform_driver amb_pinctrl_driver = {
> +	.probe	= amb_pinctrl_probe,
> +	.driver	= {
> +		.name	= "ambarella-pinctrl",
> +		.of_match_table = of_match_ptr(amb_pinctrl_dt_match),

Why of_match_ptr()?!

> +	},
> +};

-- 
With Best Regards,
Andy Shevchenko



  parent reply	other threads:[~2026-09-04 13:30 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-04  6:38 [PATCH v6 00/13] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-09-04  6:38 ` [PATCH v6 01/13] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-09-04  6:42   ` sashiko-bot
2026-09-04 22:39   ` Linus Walleij
2026-09-04  6:38 ` [PATCH v6 02/13] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-09-04  6:45   ` sashiko-bot
2026-09-04  6:38 ` [PATCH v6 03/13] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-09-04  6:45   ` sashiko-bot
2026-09-04  6:38 ` [PATCH v6 04/13] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Long Zhao via B4 Relay
2026-09-04  6:45   ` sashiko-bot
2026-09-04 22:40   ` Linus Walleij
2026-09-04  6:38 ` [PATCH v6 05/13] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-09-04  6:47   ` sashiko-bot
2026-09-04 14:45   ` Rob Herring
2026-09-04  6:38 ` [PATCH v6 06/13] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Long Zhao via B4 Relay
2026-09-04  6:42   ` sashiko-bot
2026-09-04 22:41   ` Linus Walleij
2026-09-04  6:38 ` [PATCH v6 07/13] clk: ambarella: add CV75 CCU driver Long Zhao via B4 Relay
2026-09-04  6:53   ` sashiko-bot
2026-09-04  7:44   ` Jerome Brunet
2026-09-04  9:21     ` zl020895
2026-09-04  6:38 ` [PATCH v6 08/13] gpio: regmap: support write_data_after_dir and girq Long Zhao via B4 Relay
2026-09-04  6:54   ` sashiko-bot
2026-09-04 11:55   ` Andy Shevchenko
2026-09-04  6:38 ` [PATCH v6 09/13] gpio: pl061: use gpio-regmap and add Ambarella layout Long Zhao via B4 Relay
2026-09-04  6:49   ` sashiko-bot
2026-09-04 13:14   ` Andy Shevchenko
2026-09-04  6:38 ` [PATCH v6 10/13] pinctrl: ambarella: add CV75 pin controller Long Zhao via B4 Relay
2026-09-04  6:50   ` sashiko-bot
2026-09-04 13:29   ` Andy Shevchenko [this message]
2026-09-04  6:38 ` [PATCH v6 11/13] serial: 8250_dw: add Ambarella CV75 quirks Long Zhao via B4 Relay
2026-09-04  6:51   ` sashiko-bot
2026-09-04 22:45     ` Linus Walleij
2026-09-04 22:43   ` Linus Walleij
2026-09-04  6:38 ` [PATCH v6 12/13] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-09-04  6:48   ` sashiko-bot
2026-09-04 22:45   ` Linus Walleij
2026-09-04  6:38 ` [PATCH v6 13/13] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
2026-09-04 22:45   ` Linus Walleij
2026-09-04  6:54 ` [PATCH v6 00/13] Ambarella CV75 SoC minimal bring-up Jerome Brunet
2026-09-04  6:56   ` Krzysztof Kozlowski

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