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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e9bea11b8sm13829938eec.7.2026.09.24.02.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 02:46:22 -0700 (PDT) Date: Thu, 24 Sep 2026 17:46:16 +0800 From: Shawn Guo To: Taniya Das Cc: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Bartosz Golaszewski , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: qcom: gcc: Fix GPLL enable register offset for Nord SoC Message-ID: References: <20260924-nord_gcc_offset_fix-v1-1-230ffad2dae9@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260924-nord_gcc_offset_fix-v1-1-230ffad2dae9@oss.qualcomm.com> X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDA0MCBTYWx0ZWRfX8fWW5exVEbdE OJ2Ae/kkyiQB2hmDkKZMUsqqIpIGhJXrDRzwMk6X1Uf0ZnvlwOvuy61LWnJMxzmTbY9QQ1Y85Tg 3VGUdEeQOwBXwIQ5Pr0twf8dleeGwn4= X-Proofpoint-GUID: XR9_KvMPaqxlvb7k_vxzuvtue22RAFVB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDA0MCBTYWx0ZWRfX5/y9BaJD2Qb1 4b91oCSIIZQP6IGEKc/z90NsPO8u4TqfQhUsqtJiNwYWCcYI5u7aOnuITo7bPa4ZZ3elP60dZg8 BEtda5djgZDIh+050YDfjY8ezgOCaqJPkKseflTi0Rv0gF0teSXmo/9vLroTuDcYClY5gHcjsHZ bvP1vRxfJYcRHSv2yPIyhdmdief2rYE9m7hpIC+LCxoWfRya8VxN/t1Ay7aUcpOvMwoqIIcY9uA OWu42Dz4cRNL8MPCK2L6B3uBtKEo9LqC4E1dkPur3oc0+js2fe8tLFkQ0+czt1ZHXDBFlKQGLo0 rpdx53ULJvHEpjTsi5+eEgg/AFR5EQlk42G/+aYqhCq6BHHCXCoqcpUubw75t/0J1L4TjHSyQFI URNxj7SHUEe2gyG56gff3NMIO8RYNHjNsB0cChAHxDYCXKu2F9d/8z7wnl3ipdpJZ77OKGlgvvP Q4BSmQ7US47S2bMhfeQ== X-Proofpoint-ORIG-GUID: XR9_KvMPaqxlvb7k_vxzuvtue22RAFVB X-Authority-Analysis: v=2.4 cv=fMusTpae c=1 sm=1 tr=0 ts=6ab4f170 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=7o7Fz_jXMTEYJjNRgMcA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240040 On Thu, Sep 24, 2026 at 03:09:56PM +0530, Taniya Das wrote: > The GPLLs in the North-East, North-West and South-East global clock > controllers on the Qualcomm Nord SoC were registered with a placeholder > enable register offset of 0x0. As a result the shared PLL voting register > was never programmed, leaving the PLLs' enable state uncontrolled. > > Point each GPLL at its actual GPLL_ENABLE register (0x57010 for the > North-East and South-East controllers, 0x76008 for the North-West > controller). Each PLL continues to select its own vote bit through > enable_mask. > > Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") > Signed-off-by: Taniya Das Reviewed-by: Shawn Guo