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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93cca1a433dsm240505285a.13.2026.10.02.08.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2026 08:11:53 -0700 (PDT) Date: Fri, 2 Oct 2026 11:11:51 -0400 From: Brian Masney To: Stefan =?iso-8859-1?Q?D=F6singer?= Cc: linux-clk@vger.kernel.org, Brian Masney , Conor Dooley , devicetree@vger.kernel.org, Jerome Brunet , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Manivannan Sadhasivam , Neil Armstrong , Philipp Zabel , Rob Herring , Stephen Boyd , Vinod Koul , mturquette@baylibre.com Subject: Re: [GIT PULL] clk: zte: zx297520v3 clock bindings and driver (v2) Message-ID: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.4.2 (2026-08-30) Hi Stefan, On Thu, Oct 01, 2026 at 08:39:27PM +0300, Stefan Dösinger wrote: > Hi, > > This pull request contains the device tree bindings and clock driver for > ZTE zx297520v3 boards. It contains the next step in adding support for > zx297520v3 boards: Documenting clock and reset manager hardware and > adding drivers for its PLLs and clock tree. This is v2 of the pull > request, based on v7.3-rc1 rather than clk-next. > > The patches have been reviewed and carry appropriate R-B tags by > Krzysztof Kozlowski (bindings) and Brian Masney (clk driver). > > The PR does not contain the MFD, reset and device tree patches. They > will be submitted to the MFD, reset and soc trees respectively. The > clock driver compiles without them, but won't be instantiated without > the MFD parent. > > The following changes since commit cee9395acd8043be0644b25c34bfa86623f2b935: > > Linux 7.3-rc1 (2026-08-30 13:34:40 -0700) > > are available in the Git repository at: > > https://gitlab.com/stefandoesinger/zx297520-kernel.git tags/v2-zx29-clk-for-7.4 > > for you to fetch changes up to 75e4151c9e157d84c8c6c365893ecf33d221bca5: > > clk: zte: Introduce a driver for zx297520v3 LSP clocks (2026-10-01 20:20:43 +0300) > > ---------------------------------------------------------------- > clk: zte: Add clock drivers for zx297520v3 SoC > > This tag contains the device tree bindings and clock driver for ZTE > zx297520v3 boards. It contains the next step in adding support for > zx297520v3 boards: Documenting clock and reset manager hardware and > adding drivers for its PLLs and clock tree. > > The PR does not contain the MFD, reset and device tree patches. They > will be submitted to the MFD, reset and soc trees respectively. The > clock driver compiles without them, but won't be instantiated without > the MFD parent. > > ---------------------------------------------------------------- > Stefan Dösinger (9): > dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller > dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller > dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller > clk: zte: Add Clock registration infrastructure > clk: zte: Add regmap-based clocks > clk: zte: Add zx PLL support infrastructure > clk: zte: Introduce a driver for zx297520v3 top clocks > clk: zte: Introduce a driver for zx297520v3 matrix clocks > clk: zte: Introduce a driver for zx297520v3 LSP clocks The commits in the pull have the changelog in the commit message. For example: https://gitlab.com/stefandoesinger/zx297520-kernel/-/commit/75e4151c9e157d84c8c6c365893ecf33d221bca5 I went to the last series and cherry picked the relevant commits. Brian