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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-49abdc4ccacsm1106138fac.11.2026.09.29.07.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 07:08:07 -0700 (PDT) Date: Tue, 29 Sep 2026 22:08:00 +0800 From: Shawn Guo To: Krzysztof Kozlowski Cc: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Taniya Das , Jagadeesh Kona , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] dt-bindings: clock: qcom,sm8450-videocc: Fix clock inputs for Glymur Message-ID: References: <20260924161152.1162301-1-shengchao.guo@oss.qualcomm.com> <20260924161152.1162301-2-shengchao.guo@oss.qualcomm.com> <20260929-visionary-hospitable-beaver-e2c1a5@quoll> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260929-visionary-hospitable-beaver-e2c1a5@quoll> X-Proofpoint-GUID: IWpwy3AIKXmV3-Cpdb7U1Sd5n9a8a92D X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI5MDA1NiBTYWx0ZWRfX6lKVfxJS3wec Dqg3DgGkqRQf6UiAolQ4LTnp6SL2ZwJrpTq5396bPCnnhmqN3i3zRtUaPg9ewEl7TFev6ZBf9ia to+eV/CFotng2xfXLcDoH9SOxs97LY0q3jzd3qk2iFdZPVzCXa76oob9+MpESYqfdkykpYJ6561 tBuw/KYG49O+J4YL9bd4xru3O9k2ZocPDPwB1aCHafQJDLt0tow8lR+LPDyhUpwgNMb4UNd8cxg yIziROKRcJP4d4JKPQaJJH8smRllRUfXlxSUV19VNuS8K7fPOMATvTcJWpQVs2YuAwnh+yuT1qi PK3b1Zkp51wEWc8xQbKqb80OXiDtlUVt8vZZkpDhK1lYb38z2Pi0QPAQn1Owu5ttYf4wRFcrXPG AqYxSivOON2J+C6++xjtwNpH/W/qA8zNrmiHDtmIvdzvU7OtIw80ZnpcxqykwodJSJPDJUQTW4K 4VSHLTJDxnUTl55yKHg== X-Authority-Analysis: v=2.4 cv=cokOAF4i c=1 sm=1 tr=0 ts=6abbc649 cx=c_pps a=yymyAM/LQ7lj/HqAiIiKTw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=AY5MHz9oPD_TeV_maQoA:9 a=CjuIK1q_8ugA:10 a=efpaJB4zofY2dbm2aIRb:22 X-Proofpoint-ORIG-GUID: IWpwy3AIKXmV3-Cpdb7U1Sd5n9a8a92D X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI5MDA1NiBTYWx0ZWRfX0nK4f0NpPaam sm/IQuFPEK9PIB/umx+trrJNodn0JrZB2gU1dSE1dKtnxK8WbIjoJ0MuMYwKDj9NRK/DRHEwvoj de3on3DykURkCudeA+xNR1gfZ71maxU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-29_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 adultscore=0 malwarescore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609290056 On Tue, Sep 29, 2026 at 09:57:40AM +0200, Krzysztof Kozlowski wrote: > On Fri, Sep 25, 2026 at 12:11:50AM +0800, Shawn Guo wrote: > > The schema describes exactly two clock inputs for every compatible it > > covers, a board XO and a video AHB clock from GCC. That is only true > > for part of the drivers bound to these compatibles. videocc-glymur.c, > > which handles qcom,glymur-videocc and qcom,nord-videocc, and > > videocc-sm8750.c both declare their DT inputs as DT_BI_TCXO, > > DT_BI_TCXO_AO and DT_SLEEP_CLK, and parent video_cc_sleep_clk_src on > > DT_SLEEP_CLK. > > I don't understand what you are saying here. You are mixing drivers and > compatibles. You are right! The argument was the wrong way round. What I should have written for a schema is the hardware, not the Linux driver. Sorry about that. Per the hardware documentation, the video clock controller on Glymur, Nord and SM8750 has three clock inputs: the board XO, the always-on board XO that feeds its PLL reference, and the 32 kHz chip sleep clock that sources its sleep clock generator. There is no AHB clock input on the block; the AHB clock the controller uses for itself is generated internally from the XO input. So the schema is wrong in two ways for these three compatibles: the sleep clock input cannot be described at all, and the second item is described as a clock that is not routed into the controller. I will respin with the commit messages rewritten in those terms, with no driver references. > > > > > Because the schema stops at two items, no device tree can supply the > > third input, so video_cc_sleep_clk_src can never resolve its parent > > and registers as an orphan clock. It also documents the second input > > as an AHB clock, which no device tree using these two drivers passes, > > and which those drivers would interpret as the always-on XO. > > > > Describe three inputs for the Glymur, Nord and SM8750 compatibles, > > keeping the existing two-input description for the rest. The sibling > > qcom,glymur-evacc.yaml, whose driver has the same shape, already > > documents a sleep clock this way. > > > > Fixes: ed9ca8296147 ("dt-bindings: clock: qcom: Add video clock controller on Glymur SoC") > > Fixes: b190eaea5780 ("dt-bindings: clock: qcom: Add SM8750 video clock controller") > > Are you sure that you are not reverting review like it happened this > week in IPQ? You know, the trick with reverting maintainer's review I > mentioned on DT IRC? That's definitely not my intention! I know nothing about the trick. Would you point me to the IPQ thread or the IRC discussion, so that I understand your comment better? I checked review threads for both commits. Nothing seems to be reverted here. Or if you would rather not have the Fixes tags point at those commits, I'm happy to drop them. Shawn