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[95.246.144.141]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-492d73286cdsm5497080f8f.28.2026.11.06.14.27.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 14:27:44 -0800 (PST) Date: Fri, 6 Nov 2026 23:27:38 +0100 From: Carlo Caione To: Conor Dooley Cc: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Jian Hu , Chuan Liu , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 6/7] dt-bindings: clock: Add Amlogic S7 peripherals clock controller Message-ID: References: <20261106-upstream-s7-clk-v1-0-7d501d62621f@baylibre.com> <20261106-upstream-s7-clk-v1-6-7d501d62621f@baylibre.com> <20261106-unwilling-preoccupy-156dbb310448@spud> <20261106-headband-buckwheat-fecbd459ee85@spud> X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261106-headband-buckwheat-fecbd459ee85@spud> On Fri, Nov 06, 2026 at 20:48:01 +0100, Conor Dooley wrote: > On Fri, Nov 06, 2026 at 08:34:37PM +0100, Carlo Caione wrote: > > On Fri, Nov 06, 2026 at 17:34:14 +0100, Conor Dooley wrote: > > > > > > + #include > > > > + #include > > > > + > > > > + soc { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + > > > > + clock-controller@0 { > > > > + compatible = "amlogic,s7-peripherals-clkc"; > > > > + reg = <0x0 0x0 0x0 0x49c>; > > > > > > What's with the weird numbers in this example? > > > > > > Examples don't have to be real, but when it looks like this the > > > immediate thought is that the modelling of the device might be > > > incorrec.t > > > > The numbers are actually real, but the example simply lost their context > > because I copied the node from the S7 dtsi (not yet submitted), where > > the controller sits under the APB bus node (bus@fe000000) and the bus > > ranges make the addresses relative to it. > > > > apb: bus@fe000000 { > > compatible = "simple-bus"; > > reg = <0x0 0xfe000000 0x0 0x480000>; > > #address-cells = <2>; > > #size-cells = <2>; > > ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; > > > > clkc_periphs: clock-controller@0 { > > compatible = "amlogic,s7-peripherals-clkc"; > > reg = <0x0 0x0 0x0 0x49c>; > > #clock-cells = <1>; > > ... > > > > In V2 I'll use an absolute address for the sake of clarity (PLL has the > > same issue). > > Before you do that, can you please share with me the s7 dtsi? Cos surely > you've got it in some git repo online somewhere. The S7 dtsi is already upstream at [0], the peripheral clock controller and PLL will be enabled in that DTSI with a following series after the bindings and the drivers in this set are acked, following the diffs that will be submitted: diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi index 2c204dcebbba..5f2a61f42cbd 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include / { @@ -160,6 +162,22 @@ apb: bus@fe000000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + clkc_pll: clock-controller@8000 { + compatible = "amlogic,s7-pll-clkc"; + reg = <0x0 0x8000 0x0 0x1e8>; + #clock-cells = <1>; + clocks = <&scmi_clk CLKID_TOP_PLL_OSC>, + <&scmi_clk CLKID_TOP_PLL_OSC>, + <&scmi_clk CLKID_TOP_PLL_OSC>, + <&scmi_clk CLKID_TOP_PLL_OSC>, + <&scmi_clk CLKID_HDMI_PLL_OSC>; + clock-names = "fix", + "gp0", + "hifi", + "hifi1", + "hdmi"; + }; + uart_b: serial@7a000 { compatible = "amlogic,s7-uart", "amlogic,meson-s4-uart"; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi index 5f2a61f42cbd..afc88abea301 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -162,6 +162,40 @@ apb: bus@fe000000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + clkc_periphs: clock-controller@0 { + compatible = "amlogic,s7-peripherals-clkc"; + reg = <0x0 0x0 0x0 0x49c>; + #clock-cells = <1>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV2P5>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV4>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&clkc_pll CLKID_GP0_PLL>, + <&clkc_pll CLKID_HIFI1_PLL>, + <&scmi_clk CLKID_GP1_PLL>, + <&clkc_pll CLKID_HDMI_PLL>, + <&clkc_pll CLKID_HDMI_PLL_PIX>, + <&xtal>, + <&scmi_clk CLKID_ACLKM>; + clock-names = "fclk_div2", + "fclk_div2p5", + "fclk_div3", + "fclk_div4", + "fclk_div5", + "fclk_div7", + "hifi_pll", + "gp0_pll", + "hifi1_pll", + "gp1_pll", + "hdmi_pll", + "vid_pix", + "xtal", + "axi_frcpu"; + }; + clkc_pll: clock-controller@8000 { compatible = "amlogic,s7-pll-clkc"; reg = <0x0 0x8000 0x0 0x1e8>; [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi -- Carlo Caione