From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: David Laight <david.laight.linux@gmail.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Brian Masney <masneyb@kernel.org>,
Carlo Caione <ccaione@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Brian Norris <computersforpeace@gmail.com>,
Brian Norris <briannorris@chromium.org>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Stephen Boyd <sboyd@codeaurora.org>
Subject: Re: [PATCH 1/2] clk: divider: Fix the divisor for rates above 4.29 GHz
Date: Thu, 12 Nov 2026 00:38:48 +0100 [thread overview]
Message-ID: <avT4jl9Ti52inFUN@venus> (raw)
In-Reply-To: <20261106180029.05452269@pumpkin>
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Hi,
On Fri, Nov 06, 2026 at 06:00:29PM +0000, David Laight wrote:
> On Fri, 06 Nov 2026 16:51:50 +0100
> Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> > On 2026-11-04 16:52:04-05:00, Brian Masney wrote:
> > > > DIV_ROUND_UP_ULL() takes a 32-bit divisor, so on 64-bit platforms a
> > > > requested rate above 4.29 GHz is truncated. A divider fed by a 5.94 GHz
> > > > PLL then computes a divisor of 7, not 1, for 5.94 GHz.
> > > >
> > > > Use DIV64_U64_ROUND_UP(), which takes a 64-bit divisor.
> > > >
> > > > Fixes: 9556f9dad8f5 ("clk: divider: handle integer overflow when dividing large clock rates")
> > > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > > > Signed-off-by: Carlo Caione <ccaione@baylibre.com>
> > >
> > > Reviewed-by: Brian Masney <masneyb@kernel.org>
> > >
> > > Since this is a core change to the framework, I'd also like to see what
> > > Jerome thinks before we merge this.
> >
> > I've had not problem with the change initially but then the AI told me that
> > it brings back the overflow problem fixed by 9556f9dad8f5.
> >
> > At first I thought it was crazy because it would mean parent_rate + rate is
> > more than 18 billion GHz ... BUT, a common way to ask for the maximum rate a
> > clock supports is clk_round_rate(clk, ULONG_MAX). This could trigger the overflow
> > and there are instance of this in the kernel right now.
> >
> > A way to make the calculation without the overflow could be:
> > parent_rate / rate + (parent_rate % rate ? 1 : 0)
> >
>
> You just want:
> parent_rate ? (parent_rate - 1) / rate + 1 : 0
> it is even likely here that you can assume parent_rate in non-zero.
Looks sensible. I suggest to just add this locally in
drivers/clk/clk-divider.c until another user turns up:
static unsigned long div_clk_round_up(unsigned long dividend, unsigned long divisor)
{
return dividend ? (dividend - 1) / divisor + 1 : 0;
}
-- Sebastian
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next prev parent reply other threads:[~2026-11-11 23:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-02 21:07 [PATCH 0/2] Fix clk-divider rates above 4.29 GHz on 64-bit Carlo Caione
2026-11-02 21:07 ` [PATCH 1/2] clk: divider: Fix the divisor for rates above 4.29 GHz Carlo Caione
2026-11-04 21:52 ` Brian Masney
2026-11-04 23:10 ` David Laight
2026-11-06 15:51 ` Jerome Brunet
2026-11-06 18:00 ` David Laight
2026-11-11 23:38 ` Sebastian Reichel [this message]
2026-11-02 21:07 ` [PATCH 2/2] clk: divider: test: Add tests " Carlo Caione
2026-11-04 21:52 ` Brian Masney
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