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Thu, 12 Nov 2026 15:26:19 -0800 (PST) Received: from localhost ([2a00:79e0:2e7c:8:616b:3e06:cec4:c2f9]) by smtp.gmail.com with UTF8SMTPSA id 5a478bee46e88-3795591f4f8sm1521913eec.13.2026.11.12.15.26.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Nov 2026 15:26:18 -0800 (PST) Date: Thu, 12 Nov 2026 15:26:16 -0800 From: Brian Norris To: Jerome Brunet Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Brian Masney , Jerome Brunet , Thomas Gleixner , Ulf Hansson , Philipp Zabel , Peter Griffin , devicetree@vger.kernel.org, Tudor Ambarus , =?iso-8859-1?Q?Andr=E9?= Draszik , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Radu Rendec , linux-arm-kernel@lists.infradead.org, Mariano Marciello , Douglas Anderson , linux-clk@vger.kernel.org, Jakub =?utf-8?B?R8WCb3dhY2tp?= Subject: Re: [PATCH 5/9] clk: google: Add CPM clock driver Message-ID: References: <20261026214359.3122870-1-briannorris@chromium.org> <20261026144346.5.I82dc05365979021379fe730d6d52792a87ff15ed@changeid> <179372634472.2573818.17532943286609086157.b4-review@b4> X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <179372634472.2573818.17532943286609086157.b4-review@b4> Hi Jerome, Thanks for the review, and sorry for some delay. There was a lot to dig into here. On Tue, Nov 03, 2026 at 06:19:04PM +0100, Jerome Brunet wrote: > > Google Tensor SoCs (used on Pixel phones) manage many resources > > (including most clocks) using a Central Power Manager (CPM) > > co-processor. We communicate with CPM using mailboxes, abstracted in the > > cpm_request_client(), etc., API. > > > > The clock tree is largely not represented fully by this driver, because > > CPM hides most of the divider, mux, and parent details, instead > > maintaining its own internal table of mappings for divider and mux > > values. The one exception is for some of the DPU clocks, where several > > clocks and dividers are exposed directly, and the firmware API works on > > divider values instead of clock rates. I attempt to represent this > > properly with dividers and parents, although I don't have the full > > display stack running to verify everything yet. > > > > As you say, the clock tree is not fully represented here. Beyond that, CPM > owns the clocks themselves, as the driver acknowledges by setting > CLK_GET_RATE_NOCACHE. > > The driver keeps a partial copy of CPM's state in the kernel: > > - Rate tables below hard-code what the FW has (or should have) instead > of rounding the rate, even though there seems to be a ROUND_RATE_OP_ID. Aaah, ROUND_RATE would be lovely except ... the firmware implementation has a giant "TBD" / "error: not supported" instead :( If there are major must-haves (or, very-nice-to-haves) in this firmware API, I can see if we can get them added, but that's usually easier on not-yet-launched products, whereas Pixel 10 is more than a year old already. I'll see what's possible though. > - kernel handles PLL parenting and divider math for the DP clocks, while the > firmware can also switch them to what looks like the oscillator, out of > the kernel's view. So the math is likely duplicated as well I'd have to do a little more research to be sure to what extent the firmware actually changes any of these behind the scenes. I'd imagine that for the only divider-exposed clock (DP), it probably doesn't, but I'm not sure at the moment. I get your point though; it's certainly not beautiful, and may be difficult or impossible to maintain in general. > This middle ground cannot be kept consistent. CCF assumes it knows the > topology and computes rates from it, but the firmware makes the actual > decisions. The DP clocks already show it: the tree can report a parent the > hardware does not use, and .recalc_rate()/.determine_rate() can disagree > with what CPM programmed. > > I would advise to follow a model closer SCMI. What you are doing here looks > a lot like it. > (see drivers/firmware/arm_scmi/clock.c and drivers/clk/clk-scmi.c) > > - Put the LPCM service protocol (request word layout, dst_id, timeout, > error translation) in the CPM firmware/soc driver, behind a small API > shared by clk and reset. Philipp asked for the error helper on 6/9; the > whole request encoding is common, not just the errors. I'll try to do some more sharing similar to what you're suggesting. But full disclosure: the similarities are still somewhat rare in general. Within a given service (so in this case, you're talking about CPM_COMMON_LPCM_SERVICE, used by clock, reset, and *part* of pmdomain), the protocol is largely shared. But this series also touches CPM_COMMON_LPB_SERVICE (also in pmdomain) and hints at some CPM_COMMON_PMIC_SERVICE support (RTC and PMIC); and there are at least 5 more defined servies, as well as a few other bespoke protocols. Those each have distinct request and response/status encodings. (Unfortunately.) So, I'll try to consolidate what I can, but it probably won't go super far. > - Make the clock driver a thin CCF adapter: each CPM clock is an opaque > endpoint, and gate/rate requests go to the firmware. Get rates from the > firmware (round-rate op) instead of local tables. Model no topology the As mentioned above, round-rate is a no-go :( I also don't see any way to query firmware for supported rates. Off the top of my head, the best I can come up with is sweeping through rates on SET_RATE and guessing, until we find something that doesn't return INVALID_ARGS... > kernel does not own. If parents must be exposed, the firmware should > describe them, as SCMI does, rather than the kernel hard-coding them. I also do not think topology description is possible with any existing firmware. I would think if we were revisiting how to do this more sanely, it would make sense to stop exposing the topology at all, but TBD. Anyway, thanks for your thoughts. I'll see what I can do about ROUND_RATE, but also am interested in your opinion on the best way forward with the existing firmware API. For some positive notes: The vast majority of these clocks do not actually support multiple rates (at least, not in the tables here), nor do they expose any topology. So I think I can just remove their rate table, and only rely on (1) GET_RATE or (2) SET_RATE, which will only succeed if you get the exact supported rate. On some other clocks that support multiple rates (e.g., HSIOS_MPHY_REF_TCX0_CLK), I don't believe we ever need clk_set_rate(). We only use clk_get_rate(). So, probably same story as the 1-rate tables. A few others (DSI0/DSI1) seem to never use any get/set_rate operations, at least on any Pixel drivers. So that probably can also be omitted. I think that _only_ leaves DP clocks. All in all, maybe I can strip a lot of this down quite a bit, and work on DP separately. Brian