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Fri, 18 Oct 2024 06:54:59 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49I6svSa023780 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Oct 2024 06:54:57 GMT Received: from [10.253.38.177] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 23:54:52 -0700 Message-ID: Date: Fri, 18 Oct 2024 14:54:50 +0800 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/4] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC To: Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio , , , , , , , , , , , , References: <20241015-qcom_ipq_cmnpll-v4-0-27817fbe3505@quicinc.com> <20241015-qcom_ipq_cmnpll-v4-4-27817fbe3505@quicinc.com> Content-Language: en-US From: Jie Luo In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: c5Or9K_MdDIhJ7_y1VP9h5_obojfo7KE X-Proofpoint-ORIG-GUID: c5Or9K_MdDIhJ7_y1VP9h5_obojfo7KE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410180042 On 10/18/2024 6:32 AM, Dmitry Baryshkov wrote: > On Tue, Oct 15, 2024 at 10:16:54PM +0800, Luo Jie wrote: >> The CMN PLL clock controller allows selection of an input >> clock rate from a defined set of input clock rates. It in-turn >> supplies fixed rate output clocks to the hardware blocks that >> provide ethernet functions such as PPE (Packet Process Engine) >> and connected switch or PHY, and to GCC. >> >> Signed-off-by: Luo Jie >> --- >> arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +++++- >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 +++++++++++++++++++- >> 2 files changed, 24 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> index 91e104b0f865..77e1e42083f3 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> @@ -3,7 +3,7 @@ >> * IPQ9574 RDP board common device tree source >> * >> * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. >> - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> /dts-v1/; >> @@ -164,6 +164,10 @@ &usb3 { >> status = "okay"; >> }; >> >> +&cmn_pll_ref_clk { >> + clock-frequency = <48000000>; >> +}; >> + >> &xo_board_clk { >> clock-frequency = <24000000>; >> }; >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 14c7b3a78442..93f66bb83c5a 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -3,10 +3,11 @@ >> * IPQ9574 SoC device tree source >> * >> * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. >> - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> #include >> +#include >> #include >> #include >> #include >> @@ -19,6 +20,11 @@ / { >> #size-cells = <2>; >> >> clocks { >> + cmn_pll_ref_clk: cmn-pll-ref-clk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + }; > > Which block provides this clock? If it is provided by the external XO > then it should not be a part of the SoC dtsi. The on-chip WiFi block supplies this reference clock. So keeping it in the SoC DTSI is perhaps appropriate. > >> + >> sleep_clk: sleep-clk { >> compatible = "fixed-clock"; >> #clock-cells = <0>; >> @@ -243,6 +249,18 @@ mdio: mdio@90000 { >> status = "disabled"; >> }; >> >> + cmn_pll: clock-controller@9b000 { >> + compatible = "qcom,ipq9574-cmn-pll"; >> + reg = <0x0009b000 0x800>; >> + clocks = <&cmn_pll_ref_clk>, >> + <&gcc GCC_CMN_12GPLL_AHB_CLK>, >> + <&gcc GCC_CMN_12GPLL_SYS_CLK>; >> + clock-names = "ref", "ahb", "sys"; >> + #clock-cells = <1>; >> + assigned-clocks = <&cmn_pll CMN_PLL_CLK>; >> + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; >> + }; >> + >> qfprom: efuse@a4000 { >> compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; >> reg = <0x000a4000 0x5a1>; >> >> -- >> 2.34.1 >> >