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Wed, 03 Apr 2024 07:16:39 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4337GcLg024861 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Apr 2024 07:16:38 GMT Received: from [10.218.5.19] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 3 Apr 2024 00:16:32 -0700 Message-ID: Date: Wed, 3 Apr 2024 12:46:19 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 RESEND 6/6] arm64: dts: qcom: sm8650: Add video and camera clock controllers From: Jagadeesh Kona To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Vladimir Zapolskiy , , , , , Taniya Das , Satya Priya Kakitapalli , Ajit Pandey , Imran Shaik References: <20240321092529.13362-1-quic_jkona@quicinc.com> <20240321092529.13362-7-quic_jkona@quicinc.com> <008d574f-9c9e-48c6-b64e-89fb469cbde4@quicinc.com> Content-Language: en-US In-Reply-To: <008d574f-9c9e-48c6-b64e-89fb469cbde4@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DWxmH7rUyjwJgd5YkLC4jXT5bdJ63qhi X-Proofpoint-GUID: DWxmH7rUyjwJgd5YkLC4jXT5bdJ63qhi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-03_06,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 bulkscore=0 impostorscore=0 clxscore=1015 spamscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404030048 On 3/25/2024 11:38 AM, Jagadeesh Kona wrote: > > > On 3/21/2024 6:43 PM, Dmitry Baryshkov wrote: >> On Thu, 21 Mar 2024 at 11:27, Jagadeesh Kona >> wrote: >>> >>> Add device nodes for video and camera clock controllers on Qualcomm >>> SM8650 platform. >>> >>> Signed-off-by: Jagadeesh Kona >>> --- >>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 28 ++++++++++++++++++++++++++++ >>>   1 file changed, 28 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> index 32c0a7b9aded..d862aa6be824 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> @@ -4,6 +4,8 @@ >>>    */ >>> >>>   #include >>> +#include >>> +#include >>>   #include >>>   #include >>>   #include >>> @@ -3110,6 +3112,32 @@ opp-202000000 { >>>                          }; >>>                  }; >>> >>> +               videocc: clock-controller@aaf0000 { >>> +                       compatible = "qcom,sm8650-videocc"; >>> +                       reg = <0 0x0aaf0000 0 0x10000>; >>> +                       clocks = <&bi_tcxo_div2>, >>> +                                <&gcc GCC_VIDEO_AHB_CLK>; >>> +                       power-domains = <&rpmhpd RPMHPD_MMCX>; >>> +                       required-opps = <&rpmhpd_opp_low_svs>; >> >> The required-opps should no longer be necessary. >> > > Sure, will check and remove this if not required. I checked further on this and without required-opps, if there is no vote on the power-domain & its peer from any other consumers, when runtime get is called on device, it enables the power domain just at the minimum non-zero level. But in some cases, the minimum non-zero level of power-domain could be just retention and is not sufficient for clock controller to operate, hence required-opps property is needed to specify the minimum level required on power-domain for this clock controller. Thanks, Jagadeesh > >>> +                       #clock-cells = <1>; >>> +                       #reset-cells = <1>; >>> +                       #power-domain-cells = <1>; >>> +               }; >>> + >>> +               camcc: clock-controller@ade0000 { >>> +                       compatible = "qcom,sm8650-camcc"; >>> +                       reg = <0 0x0ade0000 0 0x20000>; >>> +                       clocks = <&gcc GCC_CAMERA_AHB_CLK>, >>> +                                <&bi_tcxo_div2>, >>> +                                <&bi_tcxo_ao_div2>, >>> +                                <&sleep_clk>; >>> +                       power-domains = <&rpmhpd RPMHPD_MMCX>; >>> +                       required-opps = <&rpmhpd_opp_low_svs>; >>> +                       #clock-cells = <1>; >>> +                       #reset-cells = <1>; >>> +                       #power-domain-cells = <1>; >>> +               }; >>> + >>>                  mdss: display-subsystem@ae00000 { >>>                          compatible = "qcom,sm8650-mdss"; >>>                          reg = <0 0x0ae00000 0 0x1000>; >>> -- >>> 2.43.0 >>> >>> >> >>