From: Michael Jeanson <mjeanson@efficios.com>
To: Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: Hal Feng <hal.feng@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock
Date: Thu, 29 Aug 2024 14:12:23 -0400 [thread overview]
Message-ID: <b3511709-146e-45a8-84c4-cd7c5b0fba6b@efficios.com> (raw)
In-Reply-To: <20240826080430.179788-2-xingyu.wu@starfivetech.com>
On 2024-08-26 04:04, Xingyu Wu wrote:
> Add notifier function for PLL0 clock. In the function, the cpu_root clock
> should be operated by saving its current parent and setting a new safe
> parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
> rate, it should be switched back to the original parent clock.
>
> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Tested on a Visionfive2, on v6.11-rc5 the CPU is stuck at 1Ghz. With these 2
patches applied, CPU defaults to 1.5Ghz and can be set to 375 MHz, 500 MHz,
750 MHz.
Tested-By: Michael Jeanson <mjeanson@efficios.com>
next prev parent reply other threads:[~2024-08-29 18:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-26 8:04 [PATCH v7 0/2] Add notifier for PLL0 clock and set it 1.5GHz on the JH7110 SoC Xingyu Wu
2024-08-26 8:04 ` [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock Xingyu Wu
2024-08-27 5:49 ` Hal Feng
2024-08-28 20:19 ` Stephen Boyd
2024-08-29 5:42 ` Xingyu Wu
2024-08-29 19:24 ` Stephen Boyd
2024-08-29 18:12 ` Michael Jeanson [this message]
2024-08-26 8:04 ` [PATCH v7 2/2] riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz Xingyu Wu
2024-08-27 5:52 ` Hal Feng
2024-09-09 14:28 ` [PATCH v7 0/2] Add notifier for PLL0 clock and set it 1.5GHz on the JH7110 SoC Conor Dooley
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