[PATCH v2 7/8] arm64: dts: renesas: rzg3s-smarc: Enable SCIF3

Claudiu
2024-11-08T10:05:41Z

Enable SCIF3. It is routed on the RZ SMARC Carrier II board on SER1_UART
interface.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v2:
- none

arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index 33b9873b225a..1be21ece131e 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -9,9 +9,14 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

+#include "rzg3s-smarc-switches.h"
+
/ {
aliases {
i2c0 = &i2c0;
+#if SW_CONFIG3 == SW_ON
+ serial1 = &scif3;
+#endif
serial3 = &scif0;
mmc1 = &sdhi1;
};
@@ -102,6 +107,11 @@ scif0_pins: scif0 {
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
};

+ scif3_pins: scif3 {
+ pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */
+ <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */
+ };
+
sdhi1_pins: sd1 {
data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
@@ -141,6 +151,14 @@ &scif0 {
status = "okay";
};

+#if SW_CONFIG3 == SW_ON
+&scif3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif3_pins>;
+ status = "okay";
+};
+#endif
+
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
--
2.39.2