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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjIxMDEzNyBTYWx0ZWRfX62x8fzOzxa18 pZRHt5X4Sx8ptHKjErQlf3DUL74OjQ1dnvpmSlbsGUOvJf82V3z4IVfcgK2yEDO+WDqt0jmOTko Cogm+Vodzj0zb8VwpnHCITYbSGYcQY6BL/zppKAvnBRURH+dZV+BxZgLp/eAs/jTFEMnekquYoK gXGi5+tLK02mVE6x7ySZUeQQ4bYPb9p39/E/yGnbBQ8qeG64/57bxI1R4OTgayBtTbgSNNVzmLy 4D2OUAhxMfF3HZ5dBiDYfFxq65TTynf3X6BlFa9HJJGsVizTpH46N0DtZQ5K+1HHXBE9SaMhLnI Q6oRrDPra/DSyRK8ndI22ZLi+l41vlC26xDgYDz4uxp/WmMf6Cm5Srg8JwnA0b0DIMzeWHZlY5s ZLi/6dQ69EZj7wN2TjtFYb7mYwGhULrQng5iOGj1/uopORZirr+FPp7VQ0tduU0WPUjqlTt35gV de3sMmQxD5Wd0ircHLg== X-Proofpoint-ORIG-GUID: 6Gppn6vMWUcPwJN1xGthi0r76Q-LqZp- X-Proofpoint-Spam-Info: AW1haW4tMjYwNjIxMDEzNyBTYWx0ZWRfX8JxsmnOpzKX2 LQ4zpMhTnjaPe0xe3hcHiLfyhcVnrOzcxeQZLYEli+EzuK5LaGSpVuN9Qp5u6oF+WDCFiegNIS2 wClNFhk7BKaY1NvP/mz7IdxFWvr+2nQ= X-Authority-Analysis: v=2.4 cv=YtA/gYYX c=1 sm=1 tr=0 ts=6a37e767 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=HwFTmRh04JSsUSWzyQ2edw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=BjiN3Y7BKkz1kp-VNcwA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: 6Gppn6vMWUcPwJN1xGthi0r76Q-LqZp- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-21_01,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606210137 On 05-06-2026 03:58 pm, Krzysztof Kozlowski wrote: > On Thu, Jun 04, 2026 at 10:56:12AM +0530, Imran Shaik wrote: >> Update the QCM2290 DISPCC driver to use the DT index based parent clock >> lookup to align with the latest convention. While at it, fix the parent >> data of mdss ahb/mdp clocks to use GPLL0 main output as per HW clock plan, >> and update frequency table accordingly. Also, add the DSI1 PHY PLL input >> clocks support. >> >> Signed-off-by: Imran Shaik >> --- >> drivers/clk/qcom/dispcc-qcm2290.c | 44 ++++++++++++++++++++++++++------------- >> 1 file changed, 30 insertions(+), 14 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c >> index 1c21267ae0f7a86c1de88e888c2a990c35f0a0e0..f5dbd19d0a0334362a44f91a69229cb0f018f309 100644 >> --- a/drivers/clk/qcom/dispcc-qcm2290.c >> +++ b/drivers/clk/qcom/dispcc-qcm2290.c >> @@ -24,6 +24,18 @@ >> #include "gdsc.h" >> #include "reset.h" >> >> +enum { >> + DT_BI_TCXO, >> + DT_BI_TCXO_AO, >> + DT_GPLL0_OUT_DIV, >> + DT_GPLL0, >> + DT_DSI0_PHY_PLL_OUT_BYTECLK, >> + DT_DSI0_PHY_PLL_OUT_DSICLK, >> + DT_DSI1_PHY_PLL_OUT_BYTECLK, >> + DT_DSI1_PHY_PLL_OUT_DSICLK, >> + DT_SLEEP_CLK, >> +}; >> + >> enum { >> P_BI_TCXO, >> P_BI_TCXO_AO, >> @@ -33,6 +45,8 @@ enum { >> P_GPLL0_OUT_DIV, >> P_GPLL0_OUT_MAIN, >> P_SLEEP_CLK, >> + P_DSI1_PHY_PLL_OUT_BYTECLK, >> + P_DSI1_PHY_PLL_OUT_DSICLK, > > You just added new parents which looks like clear ABI break disguised as > "switch to DT". > > First, don't mix independent changes. Second, ABI changes must be > clearly documented and your first commits even tell false statements > claiming there is juet "extension". > > Did you test THIS EXACTLY patch on existing devices? > Yes functionally it works, as these missing external DSI1 clocks are not used but present in the DISPCC hardware. I will split the patches as suggested. Thanks, Imran