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Wed, 21 Oct 2026 01:04:17 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b4030daf5bsm547898a12.6.2026.10.21.01.04.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 01:04:15 -0700 (PDT) Message-ID: Date: Wed, 21 Oct 2026 10:04:10 +0200 X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/10] clk: qcom: cpu-8996: move off the ACD leg while the PLL speeds up To: Dmitry Baryshkov Cc: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Joonwoo Park , Imran Khan , Rajendra Nayak , Jeffrey Hugo , Maxime Ripard , Vikash Garodia , Dikshita Agarwal , Bryan O'Donoghue , Mauro Carvalho Chehab , Ilia Lin , Loic Poulain , Konrad Dybcio , Yassine Oudjana , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, Christopher Obbard References: <20261019-msm8998-fix-clocks-v1-0-370949e4d8a0@oss.qualcomm.com> <20261019-msm8998-fix-clocks-v1-5-370949e4d8a0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=YuKa1IYX c=1 sm=1 tr=0 ts=6ad87202 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=zcdO2QGPM5nA-iYd0ZEA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAzMSBTYWx0ZWRfX8ZFemOLWqNMU B5+U4sjQXvBOhRu4IXUMYOTcXC9YA1Csxnoih7+hrGsQQAIbfBRV89YZ0hA1a1ZdJKbnFf9ChLb rns/syhIAJmjKPMv5kZKoGnVSUn3LTk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAzMSBTYWx0ZWRfX3Tnenux3youT PVKT8ny3OOwH2gmKm8zehOY+vdMir2DVqdXqg5h/TgzZeEWgot75o0SrC8whuACAevp76gjVmDB 6rD9e79XRG+yWeJwRXfX0cLQ0MjEJ7F/N1keU6QRl+0ZFFoHrZ63LXBZS8aWvz5xX/XryRC/F6m wLzcaVokzmta/xsN2Ve/ia+fdRSLoMys/Oejr+phrOWlTklGSfbOlvcAX0XcB0jHjt0FVlViTTT h3thwcqS4hH/cjpAOvVCzM4pQGLHA9EtZ62uSGVbEDDp/DvKW1eNURN64TgUZAsYvK1fnC5KubY PEfrlLiPP5KS2r9TeTD/wk9wjFBvC4TU+XNMer3RZ6Cf9C+Mruj/wGkA6IKPB6ufGJykb8QkeVC 0PO0lp5Dwd3dlidDfQ3BfVVRqpvXt1olW6hcWxR17AjSLxOAKMn/np04fUgT4ExAqwzzgg2EvES aKDPLD21wqkmqzXgQzw== X-Proofpoint-GUID: ASNpBzubFBlw0PmE7axdQVojmB3b6FR7 X-Proofpoint-ORIG-GUID: ASNpBzubFBlw0PmE7axdQVojmB3b6FR7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_02,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 spamscore=0 clxscore=1015 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210031 On 10/20/26 12:10 PM, Dmitry Baryshkov wrote: > On Tue, Oct 20, 2026 at 08:52:49AM +0200, Konrad Dybcio wrote: >> On 10/19/26 3:41 PM, Dmitry Baryshkov wrote: >>> The MSM8996 CPU clusters sometimes run at half the rate they report >>> after going up between two frequencies above 600 MHz, and stay there >>> until the cluster drops below 600 MHz. The PLL, the muxes and the rest >>> of the cluster clock registers are all as expected: it is the ACD that >>> latches at half the rate when the PLL is reprogrammed to a higher rate >>> underneath it, and selecting the ACD leg again clears it. The driver >>> only moves off the ACD leg when going below 600 MHz. [...] > Downstream isn't keeping the main output below 1190.4 either. After > pre_set_rate(), cpu_clk_8996_set_rate() asks the HF mux for the target > rate, which makes mux_set_rate() set the PLL rate and then switch the mux. > So the main output follows the PLL up to new/2, e.g. 1075.2 MHz on the > way to 2150.4 MHz, on every increase above 1190.4 MHz. > > The main difference is where the cluster waits before the PLL moves: downstream > first lowers the PLL to 1190.4 MHz and parks the output at 595.2 MHz, while > this patch parks it at old/2. Both are lower than the target rate. Following > the downstream approach would mean reprogramming the PLL from inside the pmux > notifier while CCF is changing the rate of the same tree, which feels incorrect > to me. Also it wouldn't lower the peak. Acked-by: Konrad Dybcio Konrad