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[83.9.29.26]) by smtp.gmail.com with ESMTPSA id w14-20020ac2442e000000b004fbab5283ecsm1493879lfl.126.2023.07.03.04.30.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Jul 2023 04:30:39 -0700 (PDT) Message-ID: Date: Mon, 3 Jul 2023 13:30:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v3 22/28] ARM: dts: qcom: apq8064: add simple CPUFreq support Content-Language: en-US To: Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> <20230702174246.121656-23-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20230702174246.121656-23-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 2.07.2023 19:42, Dmitry Baryshkov wrote: > Declare CPU frequency-scaling properties. Each CPU has its own clock, > how all CPUs have the same OPP table. Voltage scaling is not (yet) > enabled with this patch. It will be enabled later. > > Signed-off-by: Dmitry Baryshkov > --- [...] > > + cpu_opp_table: opp-table-cpu { > + compatible = "operating-points-v2-krait-cpu"; > + nvmem-cells = <&speedbin_efuse>; > + > + /* > + * Voltage thresholds are > + */ /* Voltage thresholds are */ > + opp-384000000 { > + opp-hz = /bits/ 64 <384000000>; > + opp-peak-kBps = <384000>; > + opp-microvolt-speed0-pvs0 = <950000 950000 975000>; > + opp-microvolt-speed0-pvs1 = <925000 900000 950000>; > + opp-microvolt-speed0-pvs3 = <875000 850000 900000>; > [...] > + > memory@0 { > device_type = "memory"; > reg = <0x0 0x0>; > @@ -834,6 +1313,9 @@ qfprom: qfprom@700000 { > #address-cells = <1>; > #size-cells = <1>; > ranges; > + speedbin_efuse: speedbin@c0 { > + reg = <0x0c0 0x4>; no bits=<>? > + }; Newline between properties & subnodes and between each subnode, please lgtm otherwise, although I'm not checking these magic volt values Konrad > tsens_calib: calib@404 { > reg = <0x404 0x10>; > };