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AJvYcCWgU6pYEsfeqT6ObCZSGJFajIc/8Hgqe2a4ulFyV1fnkdcePSqp5dh+HQ3m3kxogV9DuBIXvO4a7bFa8px8rr+XGy2JGF3nc7R/ X-Gm-Message-State: AOJu0YysHbGjFQFjZ57y/+K4JxrM6qBujksPc/8YHTrdLajOKEl1iEnj U4BeaUhGy+BKIbvburgcj64DlMnZvAUB8p307eo58RsifLlELqkM0ioY2wdjCmU= X-Google-Smtp-Source: AGHT+IFupAf3+PzUtciCUtAMd59M9Bh2uNrFENRRy+veiFORUG52P2gIZyNwUtsiccta6zle1s1HIQ== X-Received: by 2002:a92:cda1:0:b0:36c:c6d:54ba with SMTP id e9e14a558f8ab-36cc1487041mr73054875ab.9.1715453232512; Sat, 11 May 2024 11:47:12 -0700 (PDT) Received: from [100.64.0.1] ([170.85.6.179]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4893700de56sm1575232173.22.2024.05.11.11.47.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 11 May 2024 11:47:11 -0700 (PDT) Message-ID: Date: Sat, 11 May 2024 13:47:08 -0500 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/2] riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz To: Xingyu Wu , Michael Turquette , Stephen Boyd , Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org References: <20240507065319.274976-1-xingyu.wu@starfivetech.com> <20240507065319.274976-3-xingyu.wu@starfivetech.com> Content-Language: en-US From: Samuel Holland In-Reply-To: <20240507065319.274976-3-xingyu.wu@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2024-05-07 1:53 AM, Xingyu Wu wrote: > CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. > But now PLL0 rate is 1GHz and the cpu frequency loads become > 333/500/500/1000MHz in fact. > > The PLL0 rate should be default set to 1.5GHz and set the > cpu_core rate to 500MHz in safe. Can this be accomplished by instead setting the CLK_SET_RATE_PARENT flag on the CPU_CORE clock? That way PLL0 is automatically set when cpufreq tries to change the CPU core frequency. Then there is no DT change and no compatibility issue. Regards, Samuel > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") > Signed-off-by: Xingyu Wu > --- > .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 45b58b6f3df8..28981b267de4 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -390,6 +390,12 @@ spi_dev0: spi@0 { > }; > }; > > +&syscrg { > + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, > + <&pllclk JH7110_PLLCLK_PLL0_OUT>; > + assigned-clock-rates = <500000000>, <1500000000>; > +}; > + > &sysgpio { > i2c0_pins: i2c0-0 { > i2c-pins {