From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8532AC67839 for ; Fri, 14 Dec 2018 07:19:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B8792086D for ; Fri, 14 Dec 2018 07:19:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="FvN4oA/T" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4B8792086D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-clk-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726998AbeLNHTF (ORCPT ); Fri, 14 Dec 2018 02:19:05 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5162 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726437AbeLNHTF (ORCPT ); Fri, 14 Dec 2018 02:19:05 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 23:19:00 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 23:19:03 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 13 Dec 2018 23:19:03 -0800 Received: from [10.19.108.132] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Dec 2018 07:19:01 +0000 Subject: Re: [PATCH V2 08/21] clk: tegra: dfll: round down voltages based on alignment To: Jon Hunter , Thierry Reding , Peter De Schrijver CC: , , References: <20181213093438.29621-1-josephl@nvidia.com> <20181213093438.29621-9-josephl@nvidia.com> From: Joseph Lo Message-ID: Date: Fri, 14 Dec 2018 15:18:59 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL108.nvidia.com (172.18.146.13) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544771940; bh=9bq3ULHjCypEe9On9Z0bgXi1soGhhN7q505XybaliWQ=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=FvN4oA/T4O2pLj5rt2IWsW5ObCpk8MWgrH3ZBhafOHr9hFBNXC1w+PRvGhI3fwZVf yBf7v6ItaGxnKmD9bbido8vMOKwwF9xwyuxbzzfuS1nzfKDZlu9Gdp+7XrUO/qC0ZQ 7zAIHzZ3LNyFV9erqk0HlERN7ZB2qSqCZ+4+t4OrZ1Jj7xo2j6MXAsPQVdYH9OPMem gTx4MiaF7XV1F6yswd1Wf9Ip2NOCUOhr8ZteShtS+ODtGOGBh8RefO9L/r80x/x8XL EQQQ6ZeZ1Thy/HSkWQthhoL7XHdf6vq+vEdISGVYGj3lEeXrHZMvdMug+4QScquJmy t82S4OguEeRKw== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 12/13/18 7:46 PM, Jon Hunter wrote: > > On 13/12/2018 09:34, Joseph Lo wrote: >> When generating the OPP table, the voltages are round down with the >> alignment from the regulator. The alignment should be applied for >> voltages look up as well. >> >> Based on the work of Penny Chiu . >> >> Signed-off-by: Joseph Lo >> --- >> *V2: >> - s/align_volt/align_step/ >> - s/reg_volt/reg_volt_id/ >> --- >> drivers/clk/tegra/clk-dfll.c | 26 +++++++++++++++----------- >> 1 file changed, 15 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c >> index 72e02898006c..b3668073d9b4 100644 >> --- a/drivers/clk/tegra/clk-dfll.c >> +++ b/drivers/clk/tegra/clk-dfll.c >> @@ -804,17 +804,17 @@ static void dfll_init_out_if(struct tegra_dfll *td) >> static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) >> { >> struct dev_pm_opp *opp; >> - int i, uv; >> + int i, align_step; >> >> opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); >> if (IS_ERR(opp)) >> return PTR_ERR(opp); >> >> - uv = dev_pm_opp_get_voltage(opp); >> + align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv; >> dev_pm_opp_put(opp); >> >> for (i = td->lut_bottom; i < td->lut_size; i++) { >> - if (td->lut_uv[i] >= uv) >> + if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step) >> return i; >> } >> >> @@ -1532,15 +1532,17 @@ static int dfll_init(struct tegra_dfll *td) >> */ >> static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) >> { >> - int i, n_voltages, reg_uV; >> + int i, n_voltages, reg_volt_id, align_step; >> >> + align_step = uV / td->soc->alignment.step_uv; >> n_voltages = regulator_count_voltages(td->vdd_reg); >> for (i = 0; i < n_voltages; i++) { >> - reg_uV = regulator_list_voltage(td->vdd_reg, i); >> - if (reg_uV < 0) >> + reg_volt_id = regulator_list_voltage(td->vdd_reg, i) / >> + td->soc->alignment.step_uv; >> + if (reg_volt_id < 0) > > I don't think that this will work. If the step is say 10000 and we > return an error code greater than -10000, we will end up with 0. Ah,I think you mean when the error code smaller than step_uv. Yes, it will be 0 in that case. I think I will just remove the 'if' clause, then it will not match anything and leave the for loop. And return error if it couldn't find anything. Same as below. Thanks. > >> break; >> >> - if (uV == reg_uV) >> + if (align_step == reg_volt_id) >> return i; >> } >> >> @@ -1554,15 +1556,17 @@ static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) >> * */ >> static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) >> { >> - int i, n_voltages, reg_uV; >> + int i, n_voltages, reg_volt_id, align_step; >> >> + align_step = uV / td->soc->alignment.step_uv; >> n_voltages = regulator_count_voltages(td->vdd_reg); >> for (i = 0; i < n_voltages; i++) { >> - reg_uV = regulator_list_voltage(td->vdd_reg, i); >> - if (reg_uV < 0) >> + reg_volt_id = regulator_list_voltage(td->vdd_reg, i) / >> + td->soc->alignment.step_uv; >> + if (reg_volt_id < 0) > > Same here. > >> break; >> >> - if (uV <= reg_uV) >> + if (align_step <= reg_volt_id) >> return i; >> } >> >> >