Re: [PATCH 08/10] arm64: dts: renesas: Add initial SoC DTSI for RZ/G2M v3.0

[Krzysztof Kozlowski <krzk@kernel.org>]

On 21/08/2026 17:03, Ayman Chaudhry wrote:
> Add initial Device Tree Source Include (DTSI) file for the Renesas
> RZ/G2M v3.0 (a.k.a. R8A774A3) SoC with basic support.
> 
> Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774a3.dtsi | 302 ++++++++++++++++++++++
>  1 file changed, 302 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3.dtsi
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a3.dtsi b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi
> new file mode 100644
> index 000000000000..f60a31612b39
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi
> @@ -0,0 +1,302 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the r8a774a3 SoC
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r8a774a3-cpg-mssr.h>
> +#include <dt-bindings/power/r8a774a3-sysc.h>
> +
> +/ {
> +	compatible = "renesas,r8a774a3";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	interrupt-parent = <&gic>;
> +
> +	cluster0_opp: opp-table-0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp-1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp-1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +	};
> +
> +	cluster1_opp: opp-table-1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-800000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp-1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp-1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&a57_0>;
> +				};
> +				core1 {
> +					cpu = <&a57_1>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&a53_0>;
> +				};
> +				core1 {
> +					cpu = <&a53_1>;
> +				};
> +				core2 {
> +					cpu = <&a53_2>;
> +				};
> +				core3 {
> +					cpu = <&a53_3>;
> +				};
> +			};
> +		};
> +
> +		a57_0: cpu@0 {
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0>;
> +			device_type = "cpu";
> +			power-domains = <&sysc R8A774A3_PD_CA57_CPU0>;
> +			next-level-cache = <&L2_CA57>;
> +			enable-method = "psci";
> +			dynamic-power-coefficient = <854>;
> +			clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>;
> +			operating-points-v2 = <&cluster0_opp>;
> +			capacity-dmips-mhz = <1024>;
> +		};
> +
> +		a57_1: cpu@1 {
> +			compatible = "arm,cortex-a57";
> +			reg = <0x1>;
> +			device_type = "cpu";
> +			power-domains = <&sysc R8A774A3_PD_CA57_CPU1>;
> +			next-level-cache = <&L2_CA57>;
> +			enable-method = "psci";
> +			clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>;
> +			operating-points-v2 = <&cluster0_opp>;
> +			capacity-dmips-mhz = <1024>;
> +		};
> +
> +		a53_0: cpu@100 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x100>;
> +			device_type = "cpu";
> +			power-domains = <&sysc R8A774A3_PD_CA53_CPU0>;
> +			next-level-cache = <&L2_CA53>;
> +			enable-method = "psci";
> +			dynamic-power-coefficient = <277>;
> +			clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
> +			operating-points-v2 = <&cluster1_opp>;
> +			capacity-dmips-mhz = <560>;
> +		};
> +
> +		a53_1: cpu@101 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x101>;
> +			device_type = "cpu";
> +			power-domains = <&sysc R8A774A3_PD_CA53_CPU1>;
> +			next-level-cache = <&L2_CA53>;
> +			enable-method = "psci";
> +			clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
> +			operating-points-v2 = <&cluster1_opp>;
> +			capacity-dmips-mhz = <560>;
> +		};
> +
> +		a53_2: cpu@102 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x102>;
> +			device_type = "cpu";
> +			power-domains = <&sysc R8A774A3_PD_CA53_CPU2>;
> +			next-level-cache = <&L2_CA53>;
> +			enable-method = "psci";
> +			clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
> +			operating-points-v2 = <&cluster1_opp>;
> +			capacity-dmips-mhz = <560>;
> +		};
> +
> +		a53_3: cpu@103 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x103>;
> +			device_type = "cpu";
> +			power-domains = <&sysc R8A774A3_PD_CA53_CPU3>;
> +			next-level-cache = <&L2_CA53>;
> +			enable-method = "psci";
> +			clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
> +			operating-points-v2 = <&cluster1_opp>;
> +			capacity-dmips-mhz = <560>;
> +		};
> +
> +		L2_CA57: cache-controller-0 {
> +			compatible = "cache";
> +			power-domains = <&sysc R8A774A3_PD_CA57_SCU>;
> +			cache-unified;
> +			cache-level = <2>;
> +		};
> +
> +		L2_CA53: cache-controller-1 {
> +			compatible = "cache";
> +			power-domains = <&sysc R8A774A3_PD_CA53_SCU>;
> +			cache-unified;
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	extal_clk: extal {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +		bootph-all;
> +	};
> +
> +	extalr_clk: extalr {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +		bootph-all;
> +	};
> +
> +	pmu_a53 {

Please, do not send us downstream code. It looks awfully like one. It's
long time fixed in all upstream platforms. Also, this causes now warnings.

Best regards,
Krzysztof