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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf2e0868sm107030666b.58.2026.01.28.02.26.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Jan 2026 02:26:52 -0800 (PST) Message-ID: Date: Wed, 28 Jan 2026 11:26:49 +0100 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/8] dt-bindings: clock: qcom: Add X1P42100 video clock controller To: Dmitry Baryshkov , Jagadeesh Kona Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio , Ajit Pandey , Imran Shaik , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260128-purwa-videocc-camcc-v1-0-b23de57df5ba@oss.qualcomm.com> <20260128-purwa-videocc-camcc-v1-1-b23de57df5ba@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=XqT3+FF9 c=1 sm=1 tr=0 ts=6979e46f cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=6d1n1Ba-E67CpG4V2ygA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: F_gimlqZnrVef_Q5aTBIhLq6f9TgUzLY X-Proofpoint-ORIG-GUID: F_gimlqZnrVef_Q5aTBIhLq6f9TgUzLY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI4MDA4NSBTYWx0ZWRfX3U3NvdRwnUJj SeMK1iAt6+wVqKX7O3x1YcHc7jzVEy0ISC2BIcwauKHMFPPs3Jm+eopl+ayIR/UdGxDddRsa5uP ury2yldmUF+p9A4I1e+AwRMNurdXCPU0dF9j15BIprlaX5WgWBaBsu30UCQxwFS9LZjeV+JMCRn cWZjY7LMFRjfe43UU5H7WFJhs9LKWreOiEAczKC35X0o4zzLTGIDbMtjUo1gRmTwvHg3nBw1+oL dfAxl7JtH2v6Lp5fZ2UYOzDoXbkzH7bh/MgF5CgYMjERaDwePp0qhlewDsOFBOAv/rvROX9ekTD IWtpWKTbzKUwDJY/cazIFQtf9cg7r7WEriOnjQcjsqBKNdvMGcEVLpzrqTaz06wBEpiPhBbO9pH cpzfkJYpH65Sx4cF4e2+Y6tPqooQhKR8KtUrT7fz69tCwuGsx2pg+zesK2AoTmZeA/T8YuiP6Wo YKGyamWxwDtiuL9fH9Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_02,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601280085 On 1/27/26 9:34 PM, Dmitry Baryshkov wrote: > On Wed, Jan 28, 2026 at 12:56:32AM +0530, Jagadeesh Kona wrote: >> X1P42100 video clock controller has most clocks same as SM8650, >> but it also has few additional clocks and resets. Add device >> tree bindings for the video clock controller on Qualcomm >> X1P42100 platform by defining these additional clocks and resets >> on top of SM8650. >> >> Signed-off-by: Jagadeesh Kona >> --- >> .../bindings/clock/qcom,sm8450-videocc.yaml | 2 ++ >> include/dt-bindings/clock/qcom,x1p42100-videocc.h | 21 +++++++++++++++++++++ >> 2 files changed, 23 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> index e6beebd6a36ee1ce213a816f60df8a76fa5c44d6..e8bf3fcad3fabc4f3b7e8e692c6c634d1aed9605 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> @@ -30,6 +30,7 @@ properties: >> - qcom,sm8650-videocc >> - qcom,sm8750-videocc >> - qcom,x1e80100-videocc >> + - qcom,x1p42100-videocc >> >> clocks: >> items: >> @@ -67,6 +68,7 @@ allOf: >> - qcom,sm8450-videocc >> - qcom,sm8550-videocc >> - qcom,sm8750-videocc >> + - qcom,x1p42100-videocc >> then: >> required: >> - required-opps >> diff --git a/include/dt-bindings/clock/qcom,x1p42100-videocc.h b/include/dt-bindings/clock/qcom,x1p42100-videocc.h >> new file mode 100644 >> index 0000000000000000000000000000000000000000..eb6c9b7264f8cbced7cfa0001903238ffa168431 >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,x1p42100-videocc.h >> @@ -0,0 +1,21 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> +/* >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >> + */ >> + >> +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H >> +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H >> + >> +#include "qcom,sm8650-videocc.h" >> + >> +/* X1P42100 introduces below new clocks and resets compared to SM8650 */ > > And then someone introduces new clocks or resets into SM8650 bindings > and this gets busted. Please extend the existing header. This is funny.. $ rg sm8450-videocc.h arch/ -l arch/arm64/boot/dts/qcom/hamoa.dtsi arch/arm64/boot/dts/qcom/sm8550.dtsi arch/arm64/boot/dts/qcom/sm8450.dtsi $ rg sm8450-videocc.h drivers/ -l drivers/clk/qcom/videocc-sm8450.c hmm! :) Checking further, we have videocc-sm8550.c catering: { .compatible = "qcom,sm8550-videocc" }, { .compatible = "qcom,sm8650-videocc" }, { .compatible = "qcom,x1e80100-videocc" }, and including qcom,sm8*6*50-videocc.h BUT it doesn't end there qcom,sm8650-videocc.h starts with #include "qcom,sm8450-videocc.h" So it's quite a matryoshka.. Konrad