From: "Arnd Bergmann" <arnd@arndb.de>
To: "Siarhei Volkau" <lis8215@gmail.com>,
"kernel test robot" <lkp@intel.com>
Cc: kbuild-all@lists.01.org,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Paul Cercueil" <paul@crapouillou.net>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
linux-serial@vger.kernel.org, linux-mips@vger.kernel.org,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>
Subject: Re: [PATCH 7/8] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs
Date: Thu, 13 Oct 2022 08:46:39 +0200 [thread overview]
Message-ID: <bb9f79d4-82a9-4790-b849-d517333ea2d4@app.fastmail.com> (raw)
In-Reply-To: <CAKNVLfaFvge4A8-QUzeq-JManpuYMGvyHXCJi-ew==CWN8-M=A@mail.gmail.com>
On Thu, Oct 13, 2022, at 8:37 AM, Siarhei Volkau wrote:
> пн, 10 окт. 2022 г. в 01:29, kernel test robot <lkp@intel.com>:
>> config: ia64-allyesconfig
>> config: arm64-randconfig-r035-20221010
>
>> > 142 #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000))
>
>> 0-DAY CI Kernel Test Service
>
> I know CKSEG1ADDR is MIPS specific, might be it needed to disable COMPILE_TEST
> on the driver?
> Since early syscon isn't mainlined yet I don't see any other way at the moment.
>
> Any suggestions on that, folks?
This looks like some setup that belongs into the bootloader. If you are
handing over the console from bootloader to kernel, the hardware should
already be in a working state, with no need to touch it during early
boot.
If you are dealing with broken bootloaders that are not under your control,
having this code in the architecture specific early boot as a fixup
would be better than putting it into the driver.
Arnd
next prev parent reply other threads:[~2022-10-13 6:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-09 18:13 [PATCH 0/8] MIPS: ingenic: Add support for the JZ4755 SoC Siarhei Volkau
2022-10-09 18:13 ` [PATCH 1/8] dt-bindings: " Siarhei Volkau
2022-10-10 14:53 ` Krzysztof Kozlowski
2022-10-10 20:18 ` Siarhei Volkau
2022-10-11 12:08 ` Krzysztof Kozlowski
2022-10-13 9:03 ` Paul Cercueil
2022-10-09 18:13 ` [PATCH 2/8] MIPS: ingenic: add new machine type MACH_JZ4755 Siarhei Volkau
2022-10-09 18:13 ` [PATCH 3/8] dt-bindings: clock: Add Ingenic JZ4755 CGU header Siarhei Volkau
2022-10-10 13:05 ` Rob Herring
2022-10-09 18:13 ` [PATCH 4/8] clk: Add Ingenic JZ4755 CGU driver Siarhei Volkau
2022-10-09 18:13 ` [PATCH 5/8] pinctrl: ingenic: JZ4755 minor bug fixes Siarhei Volkau
2022-10-17 9:46 ` Linus Walleij
2022-10-09 18:13 ` [PATCH 6/8] dmaengine: JZ4780: Add support for the JZ4755 Siarhei Volkau
2022-10-09 18:13 ` [PATCH 7/8] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs Siarhei Volkau
2022-10-10 20:20 ` Greg Kroah-Hartman
2022-10-11 18:38 ` Siarhei Volkau
[not found] ` <202210100607.YdxoR0tD-lkp@intel.com>
2022-10-13 6:37 ` Siarhei Volkau
2022-10-13 6:46 ` Arnd Bergmann [this message]
2022-10-13 9:17 ` Paul Cercueil
2022-10-13 18:56 ` Siarhei Volkau
2022-10-16 18:39 ` Siarhei Volkau
2022-10-17 9:31 ` Paul Cercueil
2022-10-19 15:19 ` Siarhei Volkau
2022-10-09 18:13 ` [PATCH 8/8] MIPS: DTS: Ingenic: Add support for the JZ4755 SoC Siarhei Volkau
2022-10-10 14:54 ` Krzysztof Kozlowski
2022-10-10 20:00 ` Siarhei Volkau
2022-10-11 12:09 ` Krzysztof Kozlowski
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