From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D86158208; Wed, 3 Apr 2024 07:23:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712129022; cv=none; b=G6LJIIAg5whlZEhkTSYCi7zHWe9TgNBR6U9BhH7riPs/vz0uQI6/Q01tTbaAduRueghhAGCeLUION0GoH0WUYlNIhP6P1zP7ApgzFL8eu4iMWdZc561GhftLqEiUv/zQqAhiyXnuzB+WTSZKzoYnXT9lTC6Mu57dSdiIw5Cc/xQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712129022; c=relaxed/simple; bh=6HqhTpg6hJ6e3zeFzvf8NRUha1X4YypuenPq4riKi2w=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=VqLaeczaygqGsxJ6ZEbp+wg8vF3LX3IV03ctzDBQ8rMwgWYZfFIuGlnIJMIOfCECIWyzwY4AzdD56KK8biuVDd/0HoVuxBeBlBJF3un4Qp35OiQPPGrW/EGWpZPmjCBAHdugT1Sr9OPwcVLuPKQ8xtM5dKUPjH605aSPVupDTLA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JnLFN5iG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JnLFN5iG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DA15C433F1; Wed, 3 Apr 2024 07:23:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712129021; bh=6HqhTpg6hJ6e3zeFzvf8NRUha1X4YypuenPq4riKi2w=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=JnLFN5iG6jR127kBF3VJGNw7pcD+kle+rRfAj4a/YIRawTPNtzjs71teD2VI/d3q8 rbnvy7DLs3lIGJ/rpPUY11FMQ39c0o1WZBFKvl2o6iKe0060p/pxuzKY85jqk3juYr qs1AEBS0RaMWoU46OYeGUCXQlZNouBf/W6nz0NeNu6DH247T82aIPsAmT3XhzUN7oH 4TKZN7qQLu7ON/kvrdJXyUsCL/aiWPjS6kil+9P6XhJvzEjI6eN81wuOuIRg5pJgKc gGwRtVbXKFbzlQ9qUhegj5T1P2+vZPfZ5diQUzMqkoDSx1ODiiEAgXFXVJIJ7U7aQB He5v/QQv4N7sg== Message-ID: Date: Wed, 3 Apr 2024 09:23:33 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] clk: starfive: pll: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz To: Xingyu Wu , Michael Turquette , Stephen Boyd , Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "devicetree@vger.kernel.org" References: <20240402090920.11627-1-xingyu.wu@starfivetech.com> <8d21b1bc-9402-41d4-bd81-c521c8a33d2d@kernel.org> Content-Language: en-US From: Krzysztof Kozlowski Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 03/04/2024 09:19, Xingyu Wu wrote: > On 03/04/2024 0:18, Krzysztof Kozlowski wrote: >> >> On 02/04/2024 11:09, Xingyu Wu wrote: >>> CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. >>> But now PLL0 rate is 1GHz and the cpu frequency loads become >>> 333/500/500/1000MHz in fact. >>> >>> So PLL0 rate should be default set to 1.5GHz. But setting the >>> PLL0 rate need certain steps: >>> >>> 1. Change the parent of cpu_root clock to OSC clock. >>> 2. Change the divider of cpu_core if PLL0 rate is higher than >>> 1.25GHz before CPUfreq boot. >>> 3. Change the parent of cpu_root clock back to PLL0 clock. >>> >>> Reviewed-by: Hal Feng >>> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 >>> SoC") >>> Signed-off-by: Xingyu Wu >>> --- >>> >>> Hi Stephen and Emil, >>> >>> This patch fixes the issue about lower rate of CPUfreq[1] by setting >>> PLL0 rate to 1.5GHz. >>> >>> In order not to affect the cpu operation, setting the PLL0 rate need >>> certain steps. The cpu_root's parent clock should be changed first. >>> And the divider of the cpu_core clock should be set to 2 so they won't >>> crash when setting 1.5GHz without voltage regulation. Due to PLL >>> driver boot earlier than SYSCRG driver, cpu_core and cpu_root clocks >>> are using by ioremap(). >>> >>> [1]: https://github.com/starfive-tech/VisionFive2/issues/55 >>> >>> Previous patch link: >>> v2: >>> https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfive >>> tech.com/ >>> v1: >>> https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfive >>> tech.com/ >>> >>> Thanks, >>> Xingyu Wu >>> --- >>> .../jh7110-starfive-visionfive-2.dtsi | 5 + >>> .../clk/starfive/clk-starfive-jh7110-pll.c | 102 ++++++++++++++++++ >> >> Please do not mix DTS and driver code. That's not really portable. DTS is being >> exported and used in other projects. > > OK, I will submit that in two patches. > >> >> ... >> >>> >>> @@ -458,6 +535,8 @@ static int jh7110_pll_probe(struct platform_device >> *pdev) >>> struct jh7110_pll_priv *priv; >>> unsigned int idx; >>> int ret; >>> + struct device_node *np; >>> + struct resource res; >>> >>> priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); >>> if (!priv) >>> @@ -489,6 +568,29 @@ static int jh7110_pll_probe(struct platform_device >> *pdev) >>> return ret; >>> } >>> >>> + priv->is_first_set = true; >>> + np = of_find_compatible_node(NULL, NULL, "starfive,jh7110-syscrg"); >> >> Your drivers should not do it. It's fragile, hides true link/dependency. >> Please use phandles. >> >> >>> + if (!np) { >>> + ret = PTR_ERR(np); >>> + dev_err(priv->dev, "failed to get syscrg node\n"); >>> + goto np_put; >>> + } >>> + >>> + ret = of_address_to_resource(np, 0, &res); >>> + if (ret) { >>> + dev_err(priv->dev, "failed to get syscrg resource\n"); >>> + goto np_put; >>> + } >>> + >>> + priv->syscrg_base = ioremap(res.start, resource_size(&res)); >>> + if (!priv->syscrg_base) >>> + ret = -ENOMEM; >> >> Why are you mapping other device's IO? How are you going to ensure synced >> access to registers? > > Because setting PLL0 rate need specific steps and use the clocks of SYSCRG. That's not a reason to map other device's IO. That could be a reason for having syscon or some other sort of relationship, like clock or reset. > But SYSCRG driver also need PLL clock to be clock source when adding clock > providers. I tried to add SYSCRG clocks in 'clocks' property in DT and use > clk_get() to get the clocks. But it could not run and crash. So I use ioremap() > instead. So instead of properly model the relationship, you entangle the drivers even more. Please come with a proper design for this. I have no clue about your hardware, but that looks like you are asynchronously configuring the same hardware in two different places. Sorry, that's poor code. Best regards, Krzysztof