Re: [PATCH v2 5/6] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 3/18/26 9:39 AM, Kathiravan Thirumoorthy wrote:
> Add initial device tree support for the Qualcomm IPQ5210 SoC and
> rdp504 board.
> 
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---

[...]

> +&sdhc {
> +	max-frequency = <192000000>;
> +	bus-width = <4>;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	pinctrl-0 = <&sdhc_default_state>;
> +	pinctrl-names = "default";
> +	status = "okay";

nit: Please keep a uniform \n before 'status', file-wide

[...]

> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&l2_0>;

Since we have PSCI, is there some sort of cpuidle?

[...]

> +		intc: interrupt-controller@b000000 {
> +			compatible = "qcom,msm-qgic2";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			reg = <0x0 0xb000000 0x0 0x1000>,  /* GICD */
> +			      <0x0 0xb002000 0x0 0x1000>,  /* GICC */
> +			      <0x0 0xb001000 0x0 0x1000>,  /* GICH */
> +			      <0x0 0xb004000 0x0 0x1000>;  /* GICV */

let's drop these comments

[...]

> +		timer@b120000 {
> +			compatible = "arm,armv7-timer-mem";
> +			reg = <0x0 0xb120000 0x0 0x1000>;

Please pad the address part of reg with leading zeroes to 8 hex digits
(i.e. 0x0b120000 etc.)

otherwise I think lgtm

Konrad