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Tue, 24 Jun 2025 00:04:42 -0700 (PDT) Message-ID: Date: Tue, 24 Jun 2025 10:04:40 +0300 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: at91: sam9x7: update pll clk ranges To: Varshini Rajendran , mturquette@baylibre.com, sboyd@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Patrice Vilchez References: <20250610084503.69749-1-varshini.rajendran@microchip.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: <20250610084503.69749-1-varshini.rajendran@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Varshini, On 10.06.2025 11:45, Varshini Rajendran wrote: > Update the min, max ranges of the PLL clocks according to the latest > datasheet to be coherent in the driver. This patch apparently solves > issues in obtaining the right sdio frequency. > > Fixes: 33013b43e271 ("clk: at91: sam9x7: add sam9x7 pmc driver") > Suggested-by: Patrice Vilchez > Signed-off-by: Varshini Rajendran > --- > drivers/clk/at91/sam9x7.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c > index cbb8b220f16b..ffab32b047a0 100644 > --- a/drivers/clk/at91/sam9x7.c > +++ b/drivers/clk/at91/sam9x7.c > @@ -61,44 +61,44 @@ static const struct clk_master_layout sam9x7_master_layout = { > > /* Fractional PLL core output range. */ > static const struct clk_range plla_core_outputs[] = { > - { .min = 375000000, .max = 1600000000 }, > + { .min = 800000000, .max = 1600000000 }, > }; > > static const struct clk_range upll_core_outputs[] = { > - { .min = 600000000, .max = 1200000000 }, > + { .min = 600000000, .max = 960000000 }, > }; > > static const struct clk_range lvdspll_core_outputs[] = { > - { .min = 400000000, .max = 800000000 }, > + { .min = 600000000, .max = 1200000000 }, > }; > > static const struct clk_range audiopll_core_outputs[] = { > - { .min = 400000000, .max = 800000000 }, > + { .min = 600000000, .max = 1200000000 }, > }; > > static const struct clk_range plladiv2_core_outputs[] = { > - { .min = 375000000, .max = 1600000000 }, > + { .min = 800000000, .max = 1600000000 }, > }; > > /* Fractional PLL output range. */ > static const struct clk_range plla_outputs[] = { > - { .min = 732421, .max = 800000000 }, > + { .min = 400000000, .max = 800000000 }, > }; > > static const struct clk_range upll_outputs[] = { > - { .min = 300000000, .max = 600000000 }, > + { .min = 300000000, .max = 480000000 }, > }; > > static const struct clk_range lvdspll_outputs[] = { > - { .min = 10000000, .max = 800000000 }, > + { .min = 175000000, .max = 550000000 }, > }; > > static const struct clk_range audiopll_outputs[] = { > - { .min = 10000000, .max = 800000000 }, > + { .min = 0, .max = 300000000 }, Is this min value something valid? Thank you, Claudiu