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[83.9.30.30]) by smtp.gmail.com with ESMTPSA id a19-20020ac25213000000b004f865fead78sm92605lfl.161.2023.06.23.18.45.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Jun 2023 18:45:04 -0700 (PDT) Message-ID: Date: Sat, 24 Jun 2023 03:45:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 03/15] dt-bindings: clock: qcom,dispcc-sm6125: Require GCC PLL0 DIV clock Content-Language: en-US To: Marijn Suijten , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Lux Aliaga References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> <20230624-sm6125-dpu-v1-3-1d5a638cebf2@somainline.org> From: Konrad Dybcio In-Reply-To: <20230624-sm6125-dpu-v1-3-1d5a638cebf2@somainline.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 24.06.2023 02:41, Marijn Suijten wrote: > The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will > be passed from DT, and should be required by the bindings. > > Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings") > Signed-off-by: Marijn Suijten > --- Ideally, you'd stick it at the bottom of the list, as the items: order is part of the ABI Konrad > Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml > index 2acf487d8a2f..11ec154503a3 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml > @@ -23,6 +23,7 @@ properties: > clocks: > items: > - description: Board XO source > + - description: GPLL0 div source from GCC > - description: Byte clock from DSI PHY0 > - description: Pixel clock from DSI PHY0 > - description: Pixel clock from DSI PHY1 > @@ -32,6 +33,7 @@ properties: > clock-names: > items: > - const: bi_tcxo > + - const: gcc_disp_gpll0_div_clk_src > - const: dsi0_phy_pll_out_byteclk > - const: dsi0_phy_pll_out_dsiclk > - const: dsi1_phy_pll_out_dsiclk > @@ -65,12 +67,14 @@ examples: > compatible = "qcom,sm6125-dispcc"; > reg = <0x5f00000 0x20000>; > clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, > <&dsi0_phy 0>, > <&dsi0_phy 1>, > <&dsi1_phy 1>, > <&dp_phy 0>, > <&dp_phy 1>; > clock-names = "bi_tcxo", > + "gcc_disp_gpll0_div_clk_src", > "dsi0_phy_pll_out_byteclk", > "dsi0_phy_pll_out_dsiclk", > "dsi1_phy_pll_out_dsiclk", >