[PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[ksk4725]

From: SeonGu Kang <ksk4725@coasia.com>

Add basic support for the Axis ARTPEC-8 SoC.
This SoC contains four Cortex-A53 CPUs and other several IPs.

Patches 1 to 10 provide the support for the clock controller,
which is similar to other Samsung SoCs.

The remaining patches provide pinctrl support and
initial device tree support.

Hakyeong Kim (9):
  dt-bindings: clock: Add ARTPEC-8 CMU bindings
  clk: samsung: Add clock PLL support for ARTPEC-8 SoC
  clk: samsung: artpec-8: Add initial clock support
  clk: samsung: artpec-8: Add clock support for CMU_CMU block
  clk: samsung: artpec-8: Add clock support for CMU_BUS block
  clk: samsung: artpec-8: Add clock support for CMU_CORE block
  clk: samsung: artpec-8: Add clock support for CMU_CPUCL block
  clk: samsung: artpec-8: Add clock support for CMU_FSYS block
  clk: samsung: artpec-8: Add clock support for CMU_PERI block

Ravi Patel (2):
  dt-bindings: clock: Add CMU bindings definitions for ARTPEC-8 platform
  dt-bindings: arm: Add Axis ARTPEC SoC platform

SeonGu Kang (3):
  dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC
  pinctrl: samsung: Add ARTPEC-8 SoC specific configuration
  arm64: dts: axis: Add initial pinctrl support

sungminpark (2):
  arm64: dts: axis: Add initial device tree support
  arm64: defconfig: Enable Axis ARTPEC SoC

 .../devicetree/bindings/arm/axis.txt          |  13 -
 .../devicetree/bindings/arm/axis.yaml         |  35 +
 .../bindings/clock/axis,artpec8-clock.yaml    | 224 +++++
 .../bindings/pinctrl/samsung,pinctrl.yaml     |   1 +
 MAINTAINERS                                   |  14 +
 arch/arm64/Kconfig.platforms                  |  13 +
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/axis/Makefile             |   4 +
 arch/arm64/boot/dts/axis/artpec-pinctrl.h     |  36 +
 arch/arm64/boot/dts/axis/artpec8-grizzly.dts  |  68 ++
 arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi | 373 ++++++++
 arch/arm64/boot/dts/axis/artpec8.dtsi         | 269 ++++++
 arch/arm64/configs/defconfig                  |   2 +
 drivers/clk/samsung/Kconfig                   |   8 +
 drivers/clk/samsung/Makefile                  |   1 +
 drivers/clk/samsung/clk-artpec8.c             | 890 ++++++++++++++++++
 drivers/clk/samsung/clk-pll.c                 | 129 ++-
 drivers/clk/samsung/clk-pll.h                 |   2 +
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    |  50 +
 drivers/pinctrl/samsung/pinctrl-exynos.h      |  10 +
 drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
 include/dt-bindings/clock/axis,artpec8-clk.h  | 122 +++
 23 files changed, 2254 insertions(+), 14 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt
 create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
 create mode 100644 arch/arm64/boot/dts/axis/Makefile
 create mode 100644 arch/arm64/boot/dts/axis/artpec-pinctrl.h
 create mode 100644 arch/arm64/boot/dts/axis/artpec8-grizzly.dts
 create mode 100644 arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/axis/artpec8.dtsi
 create mode 100644 drivers/clk/samsung/clk-artpec8.c
 create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h

-- 
2.34.1

[PATCH 01/16] dt-bindings: clock: Add CMU bindings definitions for ARTPEC-8 platform

[ksk4725]

From: Ravi Patel <ravi.patel@samsung.com>

Add device tree clock definitions constants for ARTPEC-8 platform.
ARTPEC-8 platform has separate instances for each particular CMU.
So clock IDs in this bindings header also start from 1 for each CMU block.

Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 include/dt-bindings/clock/axis,artpec8-clk.h | 122 +++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h

diff --git a/include/dt-bindings/clock/axis,artpec8-clk.h b/include/dt-bindings/clock/axis,artpec8-clk.h
new file mode 100644
index 000000000000..69adfa999e34
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec8-clk.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2022-2025  Axis Communications AB.
+ *             https://www.axis.com
+ *
+ * Device Tree binding constants for ARTPEC-8 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H
+#define _DT_BINDINGS_CLOCK_ARTPEC8_H
+
+/* CMU_CMU */
+#define PLL_SHARED0				1
+#define DOUT_PLL_SHARED0_DIV2			2
+#define DOUT_PLL_SHARED0_DIV3			3
+#define DOUT_PLL_SHARED0_DIV4			4
+#define PLL_SHARED1				5
+#define DOUT_PLL_SHARED1_DIV2			6
+#define DOUT_PLL_SHARED1_DIV3			7
+#define DOUT_PLL_SHARED1_DIV4			8
+#define PLL_AUDIO				9
+#define DOUT_CLKCMU_BUS_BUS			10
+#define DOUT_CLKCMU_BUS_DLP			11
+#define DOUT_CLKCMU_CDC_CORE			12
+#define DOUT_CLKCMU_OTP				13
+#define DOUT_CLKCMU_CORE_MAIN			14
+#define DOUT_CLKCMU_CORE_DLP			15
+#define DOUT_CLKCMU_CPUCL_SWITCH		16
+#define DOUT_CLKCMU_DLP_CORE			17
+#define DOUT_CLKCMU_FSYS_BUS			18
+#define DOUT_CLKCMU_FSYS_IP			19
+#define DOUT_CLKCMU_FSYS_SCAN0			20
+#define DOUT_CLKCMU_FSYS_SCAN1			21
+#define DOUT_CLKCMU_GPU_3D			22
+#define DOUT_CLKCMU_GPU_2D			23
+#define DOUT_CLKCMU_IMEM_ACLK			24
+#define DOUT_CLKCMU_IMEM_JPEG			25
+#define DOUT_CLKCMU_MIF_SWITCH			26
+#define DOUT_CLKCMU_MIF_BUSP			27
+#define DOUT_CLKCMU_PERI_DISP			28
+#define DOUT_CLKCMU_PERI_IP			29
+#define DOUT_CLKCMU_PERI_AUDIO			30
+#define DOUT_CLKCMU_RSP_CORE			31
+#define DOUT_CLKCMU_TRFM_CORE			32
+#define DOUT_CLKCMU_VCA_ACE			33
+#define DOUT_CLKCMU_VCA_OD			34
+#define DOUT_CLKCMU_VIO_CORE			35
+#define DOUT_CLKCMU_VIO_AUDIO			36
+#define DOUT_CLKCMU_VIP0_CORE			37
+#define DOUT_CLKCMU_VIP1_CORE			38
+#define DOUT_CLKCMU_VPP_CORE			39
+
+/* CMU_BUS */
+#define MOUT_CLK_BUS_ACLK_USER			1
+#define MOUT_CLK_BUS_DLP_USER			2
+#define DOUT_CLK_BUS_PCLK			3
+
+/* CMU_CORE */
+#define MOUT_CLK_CORE_ACLK_USER			1
+#define MOUT_CLK_CORE_DLP_USER			2
+#define DOUT_CLK_CORE_PCLK			3
+
+/* CMU_CPUCL */
+#define PLL_CPUCL				1
+#define MOUT_CLK_CPUCL_PLL			2
+#define MOUT_CLKCMU_CPUCL_SWITCH_USER		3
+#define DOUT_CLK_CPUCL_CPU			4
+#define DOUT_CLK_CLUSTER_ACLK			5
+#define DOUT_CLK_CLUSTER_PCLKDBG		6
+#define DOUT_CLK_CLUSTER_CNTCLK			7
+#define DOUT_CLK_CLUSTER_ATCLK			8
+#define DOUT_CLK_CPUCL_PCLK			9
+#define DOUT_CLK_CPUCL_CMUREF			10
+#define DOUT_CLK_CPUCL_DBG			11
+#define DOUT_CLK_CPUCL_PCLKDBG			12
+
+/* CMU_FSYS */
+#define PLL_FSYS				1
+#define MOUT_FSYS_SCAN0_USER			2
+#define MOUT_FSYS_SCAN1_USER			3
+#define MOUT_FSYS_BUS_USER			4
+#define MOUT_FSYS_MMC_USER			5
+#define DOUT_FSYS_PCIE_PIPE			6
+#define DOUT_FSYS_ADC				7
+#define DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL	8
+#define DOUT_FSYS_EQOS_INT125			9
+#define DOUT_FSYS_OTP_MEM			10
+#define DOUT_FSYS_SCLK_UART			11
+#define DOUT_FSYS_EQOS_25			12
+#define DOUT_FSYS_EQOS_2p5			13
+#define DOUT_FSYS_BUS300			14
+#define DOUT_FSYS_BUS_QSPI			15
+#define DOUT_FSYS_MMC_CARD0			16
+#define DOUT_FSYS_MMC_CARD1			17
+#define DOUT_SCAN_CLK_FSYS_125			18
+#define DOUT_FSYS_QSPI				19
+#define DOUT_FSYS_SFMC_NAND			20
+#define DOUT_SCAN_CLK_FSYS_MMC			21
+
+/* CMU_IMEM */
+#define MOUT_IMEM_ACLK_USER			1
+#define MOUT_IMEM_GIC_CA53			2
+#define MOUT_IMEM_GIC_CA5			3
+#define MOUT_IMEM_JPEG_USER			4
+
+/* CMU_PERI */
+#define MOUT_PERI_IP_USER			1
+#define MOUT_PERI_AUDIO_USER			2
+#define MOUT_PERI_I2S0				3
+#define MOUT_PERI_I2S1				4
+#define MOUT_PERI_DISP_USER			5
+#define DOUT_PERI_SPI				6
+#define DOUT_PERI_UART1				7
+#define DOUT_PERI_UART2				8
+#define DOUT_PERI_PCLK				9
+#define DOUT_PERI_I2S0				10
+#define DOUT_PERI_I2S1				11
+#define DOUT_PERI_DSIM				12
+
+#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */
-- 
2.34.1

Re: [PATCH 01/16] dt-bindings: clock: Add CMU bindings definitions for ARTPEC-8 platform

[Krzysztof Kozlowski]

On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> From: Ravi Patel <ravi.patel@samsung.com>
> 
> Add device tree clock definitions constants for ARTPEC-8 platform.
> ARTPEC-8 platform has separate instances for each particular CMU.
> So clock IDs in this bindings header also start from 1 for each CMU block.
> 
> Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> ---
>  include/dt-bindings/clock/axis,artpec8-clk.h | 122 +++++++++++++++++++
>  1 file changed, 122 insertions(+)
>  create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h

This is not a separate commit, squash with bindings.

Best regards,
Krzysztof

Re: [PATCH 01/16] dt-bindings: clock: Add CMU bindings definitions for ARTPEC-8 platform

[Hakyeong Kim]

On Thu, 2025-07-10 at 09:07 +0200, Krzysztof Kozlowski wrote:
> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> > From: Ravi Patel <ravi.patel@samsung.com>
> > 
> > Add device tree clock definitions constants for ARTPEC-8 platform.
> > ARTPEC-8 platform has separate instances for each particular CMU.
> > So clock IDs in this bindings header also start from 1 for each CMU
> > block.
> > 
> > Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> > ---
> >  include/dt-bindings/clock/axis,artpec8-clk.h | 122
> > +++++++++++++++++++
> >  1 file changed, 122 insertions(+)
> >  create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h
> 
> This is not a separate commit, squash with bindings.

Ok, I will merge patch 01 and 02 into single patch.

Thanks,
Hakyeong Kim

> 
> Best regards,
> Krzysztof

[PATCH 02/16] dt-bindings: clock: Add ARTPEC-8 CMU bindings

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add dt-schema for ARTPEC-8 SoC clock controller.

Add device-tree binding definitions for following CMU blocks:
- CMU_CMU
- CMU_BUS
- CMU_CORE
- CMU_CPUCL
- CMU_FSYS
- CMU_IMEM
- CMU_PERI

Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 .../bindings/clock/axis,artpec8-clock.yaml    | 224 ++++++++++++++++++
 1 file changed, 224 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml

diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
new file mode 100644
index 000000000000..baacea10599b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
@@ -0,0 +1,224 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axis ARTPEC-8 SoC clock controller
+
+maintainers:
+  - Jesper Nilsson <jesper.nilsson@axis.com>
+
+description: |
+  ARTPEC-8 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. The root clock in that root tree
+  is an external clock: OSCCLK (25 MHz). This external clock must be defined
+  as a fixed-rate clock in dts.
+
+  CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other clocks of function blocks (other CMUs) are usually
+  derived from CMU_CMU.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'include/dt-bindings/clock/axis,artpec8-clk.h' header.
+
+properties:
+  compatible:
+    enum:
+      - axis,artpec8-cmu-cmu
+      - axis,artpec8-cmu-bus
+      - axis,artpec8-cmu-core
+      - axis,artpec8-cmu-cpucl
+      - axis,artpec8-cmu-fsys
+      - axis,artpec8-cmu-imem
+      - axis,artpec8-cmu-peri
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+  - clock-names
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: axis,artpec8-cmu-cmu
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+
+        clock-names:
+          items:
+            - const: fin_pll
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: axis,artpec8-cmu-bus
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_BUS BUS clock (from CMU_CMU)
+            - description: CMU_BUS DLP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_clkcmu_bus_bus
+            - const: dout_clkcmu_bus_dlp
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: axis,artpec8-cmu-core
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_CORE main clock (from CMU_CMU)
+            - description: CMU_CORE DLP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_clkcmu_core_main
+            - const: dout_clkcmu_core_dlp
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: axis,artpec8-cmu-cpucl
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_CPUCL switch clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_clkcmu_cpucl_switch
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: axis,artpec8-cmu-fsys
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_FSYS SCAN0 clock (from CMU_CMU)
+            - description: CMU_FSYS SCAN1 clock (from CMU_CMU)
+            - description: CMU_FSYS BUS clock (from CMU_CMU)
+            - description: CMU_FSYS IP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_clkcmu_fsys_scan0
+            - const: dout_clkcmu_fsys_scan1
+            - const: dout_clkcmu_fsys_bus
+            - const: dout_clkcmu_fsys_ip
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: axis,artpec8-cmu-imem
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_IMEM ACLK clock (from CMU_CMU)
+            - description: CMU_IMEM JPEG clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_clkcmu_imem_aclk
+            - const: dout_clkcmu_imem_jpeg
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: axis,artpec8-cmu-peri
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_PERI IP clock (from CMU_CMU)
+            - description: CMU_PERI AUDIO clock (from CMU_CMU)
+            - description: CMU_PERI DISP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: dout_clkcmu_peri_ip
+            - const: dout_clkcmu_peri_audio
+            - const: dout_clkcmu_peri_disp
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_FSYS
+  - |
+    #include <dt-bindings/clock/axis,artpec8-clk.h>
+
+    cmu_fsys: clock-controller@16c10000 {
+        compatible = "axis,artpec8-cmu-fsys";
+        reg = <0x16c10000 0x4000>;
+        #clock-cells = <1>;
+        clocks = <&fin_pll>,
+                 <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>,
+                 <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>,
+                 <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>,
+                 <&cmu_cmu DOUT_CLKCMU_FSYS_IP>;
+        clock-names = "fin_pll",
+                      "dout_clkcmu_fsys_scan0",
+                      "dout_clkcmu_fsys_scan1",
+                      "dout_clkcmu_fsys_bus",
+                      "dout_clkcmu_fsys_ip";
+    };
+
+...
-- 
2.34.1

Re: [PATCH 02/16] dt-bindings: clock: Add ARTPEC-8 CMU bindings

[Krzysztof Kozlowski]

On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> From: Hakyeong Kim <hgkim05@coasia.com>
> 
> Add dt-schema for ARTPEC-8 SoC clock controller.
> 
> Add device-tree binding definitions for following CMU blocks:
> - CMU_CMU
> - CMU_BUS
> - CMU_CORE
> - CMU_CPUCL
> - CMU_FSYS
> - CMU_IMEM
> - CMU_PERI
> 
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>

Confusing order, unless you really understand this, but considering you
did not add your own SoB I claim you do not understand this. What does
Ravi's SoB mean here?

> ---
>  .../bindings/clock/axis,artpec8-clock.yaml    | 224 ++++++++++++++++++
>  1 file changed, 224 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
> new file mode 100644
> index 000000000000..baacea10599b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
> @@ -0,0 +1,224 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Axis ARTPEC-8 SoC clock controller
> +
> +maintainers:
> +  - Jesper Nilsson <jesper.nilsson@axis.com>
> +
> +description: |
> +  ARTPEC-8 clock controller is comprised of several CMU units, generating
> +  clocks for different domains. Those CMU units are modeled as separate device
> +  tree nodes, and might depend on each other. The root clock in that root tree
> +  is an external clock: OSCCLK (25 MHz). This external clock must be defined
> +  as a fixed-rate clock in dts.
> +
> +  CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
> +  dividers; all other clocks of function blocks (other CMUs) are usually
> +  derived from CMU_CMU.
> +
> +  Each clock is assigned an identifier and client nodes can use this identifier
> +  to specify the clock which they consume. All clocks available for usage
> +  in clock consumer nodes are defined as preprocessor macros in
> +  'include/dt-bindings/clock/axis,artpec8-clk.h' header.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - axis,artpec8-cmu-cmu
> +      - axis,artpec8-cmu-bus
> +      - axis,artpec8-cmu-core
> +      - axis,artpec8-cmu-cpucl
> +      - axis,artpec8-cmu-fsys
> +      - axis,artpec8-cmu-imem
> +      - axis,artpec8-cmu-peri
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 5
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 5
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1

reg goes second, after compatible (Samsung bindings are not the best
example because I converted them long time ago before many coding style
practices were encouraged)

> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"
> +  - clocks
> +  - clock-names
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:

Drop contains.

> +            const: axis,artpec8-cmu-cmu
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (25 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: fin_pll
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: axis,artpec8-cmu-bus
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (25 MHz)
> +            - description: CMU_BUS BUS clock (from CMU_CMU)
> +            - description: CMU_BUS DLP clock (from CMU_CMU)
> +
> +        clock-names:
> +          items:
> +            - const: fin_pll
> +            - const: dout_clkcmu_bus_bus
> +            - const: dout_clkcmu_bus_dlp

All these names should be changed to match what is the input. Look at
latest bindings, we moved away from that style.



Best regards,
Krzysztof

Re: [PATCH 02/16] dt-bindings: clock: Add ARTPEC-8 CMU bindings

[Hakyeong Kim]

On Thu, 2025-07-10 at 09:10 +0200, Krzysztof Kozlowski wrote:
> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> > From: Hakyeong Kim <hgkim05@coasia.com>
> > 
> > Add dt-schema for ARTPEC-8 SoC clock controller.
> > 
> > Add device-tree binding definitions for following CMU blocks:
> > - CMU_CMU
> > - CMU_BUS
> > - CMU_CORE
> > - CMU_CPUCL
> > - CMU_FSYS
> > - CMU_IMEM
> > - CMU_PERI
> > 
> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> > Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
> 
> Confusing order, unless you really understand this, but considering
> you
> did not add your own SoB I claim you do not understand this. What
> does
> Ravi's SoB mean here?

Ok, I will update the SoB section in all the patches.

> 
> > ---
> >  .../bindings/clock/axis,artpec8-clock.yaml    | 224
> > ++++++++++++++++++
> >  1 file changed, 224 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8-
> > clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec8-
> > clock.yaml
> > new file mode 100644
> > index 000000000000..baacea10599b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/axis,artpec8-
> > clock.yaml
> > @@ -0,0 +1,224 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Axis ARTPEC-8 SoC clock controller
> > +
> > +maintainers:
> > +  - Jesper Nilsson <jesper.nilsson@axis.com>
> > +
> > +description: |
> > +  ARTPEC-8 clock controller is comprised of several CMU units,
> > generating
> > +  clocks for different domains. Those CMU units are modeled as
> > separate device
> > +  tree nodes, and might depend on each other. The root clock in
> > that root tree
> > +  is an external clock: OSCCLK (25 MHz). This external clock must
> > be defined
> > +  as a fixed-rate clock in dts.
> > +
> > +  CMU_CMU is a top-level CMU, where all base clocks are prepared
> > using PLLs and
> > +  dividers; all other clocks of function blocks (other CMUs) are
> > usually
> > +  derived from CMU_CMU.
> > +
> > +  Each clock is assigned an identifier and client nodes can use
> > this identifier
> > +  to specify the clock which they consume. All clocks available
> > for usage
> > +  in clock consumer nodes are defined as preprocessor macros in
> > +  'include/dt-bindings/clock/axis,artpec8-clk.h' header.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - axis,artpec8-cmu-cmu
> > +      - axis,artpec8-cmu-bus
> > +      - axis,artpec8-cmu-core
> > +      - axis,artpec8-cmu-cpucl
> > +      - axis,artpec8-cmu-fsys
> > +      - axis,artpec8-cmu-imem
> > +      - axis,artpec8-cmu-peri
> > +
> > +  clocks:
> > +    minItems: 1
> > +    maxItems: 5
> > +
> > +  clock-names:
> > +    minItems: 1
> > +    maxItems: 5
> > +
> > +  "#clock-cells":
> > +    const: 1
> > +
> > +  reg:
> > +    maxItems: 1
> 
> reg goes second, after compatible (Samsung bindings are not the best
> example because I converted them long time ago before many coding
> style
> practices were encouraged)

Ok, I will move the reg property.

> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - "#clock-cells"
> > +  - clocks
> > +  - clock-names
> > +
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> 
> Drop contains.

Ok, I will remove the contains wherever applicable.

> 
> > +            const: axis,artpec8-cmu-cmu
> > +
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: External reference clock (25 MHz)
> > +
> > +        clock-names:
> > +          items:
> > +            - const: fin_pll
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: axis,artpec8-cmu-bus
> > +
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: External reference clock (25 MHz)
> > +            - description: CMU_BUS BUS clock (from CMU_CMU)
> > +            - description: CMU_BUS DLP clock (from CMU_CMU)
> > +
> > +        clock-names:
> > +          items:
> > +            - const: fin_pll
> > +            - const: dout_clkcmu_bus_bus
> > +            - const: dout_clkcmu_bus_dlp
> 
> All these names should be changed to match what is the input. Look at
> latest bindings, we moved away from that style.

Ok, I will modify clock-names to "bus" and "dlp" and will update at the
other related places also.

Thanks,
Hakyeong Kim

> 
> 
> 
> Best regards,
> Krzysztof

[PATCH 03/16] clk: samsung: Add clock PLL support for ARTPEC-8 SoC

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add below clock PLL support for ARTPEC-8 SoC platform:
- pll_1017x
- pll_1031x

Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 drivers/clk/samsung/clk-pll.c | 129 +++++++++++++++++++++++++++++++++-
 drivers/clk/samsung/clk-pll.h |   2 +
 2 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index fe8abe442c51..3337483ff8b8 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -17,6 +17,7 @@
 #include "clk.h"
 #include "clk-pll.h"
 
+#define PLL_TIMEOUT_MS		10U
 #define PLL_TIMEOUT_US		20000U
 #define PLL_TIMEOUT_LOOPS	1000000U
 
@@ -273,7 +274,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	}
 
 	/* Set PLL lock time. */
-	if (pll->type == pll_142xx)
+	if (pll->type == pll_142xx || pll->type == pll_1017x)
 		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
 			pll->lock_reg);
 	else
@@ -1325,6 +1326,125 @@ static const struct clk_ops samsung_pll531x_clk_ops = {
 	.recalc_rate = samsung_pll531x_recalc_rate,
 };
 
+/*
+ * PLL1031X Clock Type
+ */
+#define PLL1031X_LOCK_FACTOR	(500)
+
+#define PLL1031X_MDIV_MASK	(0x3ff)
+#define PLL1031X_PDIV_MASK	(0x3f)
+#define PLL1031X_SDIV_MASK	(0x7)
+#define PLL1031X_MDIV_SHIFT	(16)
+#define PLL1031X_PDIV_SHIFT	(8)
+#define PLL1031X_SDIV_SHIFT	(0)
+
+#define PLL1031X_KDIV_MASK	(0xffff)
+#define PLL1031X_KDIV_SHIFT	(0)
+#define PLL1031X_MFR_MASK	(0x3f)
+#define PLL1031X_MRR_MASK	(0x1f)
+#define PLL1031X_MFR_SHIFT	(16)
+#define PLL1031X_MRR_SHIFT	(24)
+
+static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw,
+						  unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3;
+	u64 fvco = parent_rate;
+
+	pll_con0 = readl_relaxed(pll->con_reg);
+	pll_con3 = readl_relaxed(pll->con_reg + 0xc);
+	mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK;
+	kdiv = (pll_con3 & PLL1031X_KDIV_MASK);
+
+	fvco *= (mdiv << PLL1031X_MDIV_SHIFT) + kdiv;
+	do_div(fvco, (pdiv << sdiv));
+	fvco >>= PLL1031X_MDIV_SHIFT;
+
+	return (unsigned long)fvco;
+}
+
+static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3,
+					const struct samsung_pll_rate_table *rate)
+{
+	u32 old_mdiv, old_pdiv, old_kdiv;
+
+	old_mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
+	old_pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
+	old_kdiv = (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK;
+
+	return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv ||
+		old_kdiv != rate->kdiv);
+}
+
+static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drate,
+				     unsigned long prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	const struct samsung_pll_rate_table *rate;
+	u32 con0, con3;
+
+	/* Get required rate settings from table */
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+		       drate, clk_hw_get_name(hw));
+		return -EINVAL;
+	}
+
+	con0 = readl_relaxed(pll->con_reg);
+	con3 = readl_relaxed(pll->con_reg + 0xc);
+
+	if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) {
+		/* If only s change, change just s value only */
+		con0 &= ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT);
+		con0 |= rate->sdiv << PLL1031X_SDIV_SHIFT;
+		writel_relaxed(con0, pll->con_reg);
+
+		return 0;
+	}
+
+	/* Set PLL lock time. */
+	writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg);
+
+	/* Set PLL M, P, and S values. */
+	con0 &= ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) |
+		  (PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) |
+		  (PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT));
+
+	con0 |= (rate->mdiv << PLL1031X_MDIV_SHIFT) |
+		(rate->pdiv << PLL1031X_PDIV_SHIFT) |
+		(rate->sdiv << PLL1031X_SDIV_SHIFT);
+
+	/* Set PLL K, MFR and MRR values. */
+	con3 = readl_relaxed(pll->con_reg + 0xc);
+	con3 &= ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) |
+		  (PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) |
+		  (PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT));
+	con3 |= (rate->kdiv << PLL1031X_KDIV_SHIFT) |
+		(rate->mfr << PLL1031X_MFR_SHIFT) |
+		(rate->mrr << PLL1031X_MRR_SHIFT);
+
+	/* Write configuration to PLL */
+	writel_relaxed(con0, pll->con_reg);
+	writel_relaxed(con3, pll->con_reg + 0xc);
+
+	/* Wait for PLL lock if the PLL is enabled */
+	return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
+}
+
+static const struct clk_ops samsung_pll1031x_clk_ops = {
+	.recalc_rate = samsung_pll1031x_recalc_rate,
+	.round_rate = samsung_pll_round_rate,
+	.set_rate = samsung_pll1031x_set_rate,
+};
+
+static const struct clk_ops samsung_pll1031x_clk_min_ops = {
+	.recalc_rate = samsung_pll1031x_recalc_rate,
+};
+
 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 				const struct samsung_pll_clock *pll_clk)
 {
@@ -1373,6 +1493,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	case pll_1451x:
 	case pll_1452x:
 	case pll_142xx:
+	case pll_1017x:
 		pll->enable_offs = PLL35XX_ENABLE_SHIFT;
 		pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
 		if (!pll->rate_table)
@@ -1468,6 +1589,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	case pll_4311:
 		init.ops = &samsung_pll531x_clk_ops;
 		break;
+	case pll_1031x:
+		if (!pll->rate_table)
+			init.ops = &samsung_pll1031x_clk_min_ops;
+		else
+			init.ops = &samsung_pll1031x_clk_ops;
+		break;
 	default:
 		pr_warn("%s: Unknown pll type for pll clk %s\n",
 			__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index e9a5f8e0e0a3..6c8bb7f26da5 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -49,6 +49,8 @@ enum samsung_pll_type {
 	pll_0718x,
 	pll_0732x,
 	pll_4311,
+	pll_1017x,
+	pll_1031x,
 };
 
 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
-- 
2.34.1

[PATCH 04/16] clk: samsung: artpec-8: Add initial clock support

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add initial clock support for ARTPEC-8 SoC which is required
for enabling basic clock management.

Add clock support for below CMU block in ARTPEC-8 SoC:
 - CMU_IMEM

Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 drivers/clk/samsung/Kconfig       |  8 ++++
 drivers/clk/samsung/Makefile      |  1 +
 drivers/clk/samsung/clk-artpec8.c | 62 +++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-artpec8.c

diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 76a494e95027..289591b403ad 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
 	select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
 	select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
 	select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
+	select ARTPEC8_COMMON_CLK if ARM64 && ARCH_ARTPEC8
 
 config S3C64XX_COMMON_CLK
 	bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
@@ -102,3 +103,10 @@ config TESLA_FSD_COMMON_CLK
 	help
 	  Support for the clock controller present on the Tesla FSD SoC.
 	  Choose Y here only if you build for this SoC.
+
+config ARTPEC8_COMMON_CLK
+	bool "Axis ARTPEC-8 clock controller support" if COMPILE_TEST
+	depends on COMMON_CLK_SAMSUNG
+	help
+	  Support for the clock controller present on the Axis ARTPEC-8 SoC.
+	  Choose Y here only if you are building for the Axis ARTPEC-8 SoC.
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b77fe288e4bb..473eb08fc8fc 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -3,6 +3,7 @@
 # Samsung Clock specific Makefile
 #
 
+obj-$(CONFIG_ARTPEC8_COMMON_CLK)	+= clk-artpec8.o
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o clk-cpu.o
 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK)	+= clk-exynos3250.o
 obj-$(CONFIG_EXYNOS_4_COMMON_CLK)	+= clk-exynos4.o
diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c
new file mode 100644
index 000000000000..11a48b2fcc09
--- /dev/null
+++ b/drivers/clk/samsung/clk-artpec8.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2022-2025  Axis Communications AB.
+ *             https://www.axis.com
+ *
+ * Common Clock Framework support for ARTPEC-8 SoC.
+ */
+
+#include <linux/clk-provider.h>
+#include <dt-bindings/clock/axis,artpec8-clk.h>
+
+#include "clk.h"
+
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CMU_IMEM_NR_CLK			(MOUT_IMEM_JPEG_USER + 1)
+
+/* Register Offset definitions for CMU_IMEM (0x10010000) */
+#define PLL_CON0_MUX_CLK_IMEM_ACLK_USER			0x0100
+#define PLL_CON0_MUX_CLK_IMEM_JPEG_USER			0x0120
+#define MUX_CLK_IMEM_GIC_CA53				0x1000
+#define MUX_CLK_IMEM_GIC_CA5				0x1008
+
+static const unsigned long cmu_imem_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLK_IMEM_ACLK_USER,
+	PLL_CON0_MUX_CLK_IMEM_JPEG_USER,
+	MUX_CLK_IMEM_GIC_CA53,
+	MUX_CLK_IMEM_GIC_CA5,
+};
+
+PNAME(mout_imem_aclk_user_p) = { "fin_pll", "dout_clkcmu_imem_aclk" };
+PNAME(mout_imem_gic_ca53_p) = { "mout_imem_aclk_user", "fin_pll" };
+PNAME(mout_imem_gic_ca5_p) = { "mout_imem_aclk_user", "fin_pll" };
+PNAME(mout_imem_jpeg_user_p) = { "fin_pll", "dout_clkcmu_imem_jpeg" };
+
+static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst = {
+	MUX(MOUT_IMEM_ACLK_USER, "mout_imem_aclk_user",
+	    mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1),
+	MUX(MOUT_IMEM_GIC_CA53, "mout_imem_gic_ca53",
+	    mout_imem_gic_ca53_p, MUX_CLK_IMEM_GIC_CA53, 0, 1),
+	MUX(MOUT_IMEM_GIC_CA5, "mout_imem_gic_ca5",
+	    mout_imem_gic_ca5_p, MUX_CLK_IMEM_GIC_CA5, 0, 1),
+	MUX(MOUT_IMEM_JPEG_USER, "mout_imem_jpeg_user",
+	    mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1),
+};
+
+static const struct samsung_cmu_info cmu_imem_info __initconst = {
+	.mux_clks		= cmu_imem_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_imem_mux_clks),
+	.nr_clk_ids		= CMU_IMEM_NR_CLK,
+	.clk_regs		= cmu_imem_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_imem_clk_regs),
+};
+
+static void __init artpec8_clk_cmu_imem_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &cmu_imem_info);
+}
+
+CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem",
+	       artpec8_clk_cmu_imem_init);
-- 
2.34.1

Re: [PATCH 04/16] clk: samsung: artpec-8: Add initial clock support

[Krzysztof Kozlowski]

On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> From: Hakyeong Kim <hgkim05@coasia.com>
> 
> Add initial clock support for ARTPEC-8 SoC which is required
> for enabling basic clock management.
> 
> Add clock support for below CMU block in ARTPEC-8 SoC:
>  - CMU_IMEM
> 
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
> ---
>  drivers/clk/samsung/Kconfig       |  8 ++++
>  drivers/clk/samsung/Makefile      |  1 +
>  drivers/clk/samsung/clk-artpec8.c | 62 +++++++++++++++++++++++++++++++
>  3 files changed, 71 insertions(+)
>  create mode 100644 drivers/clk/samsung/clk-artpec8.c
> 
> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
> index 76a494e95027..289591b403ad 100644
> --- a/drivers/clk/samsung/Kconfig
> +++ b/drivers/clk/samsung/Kconfig
> @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
>  	select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
>  	select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
>  	select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> +	select ARTPEC8_COMMON_CLK if ARM64 && ARCH_ARTPEC8

Here and:

>  
>  config S3C64XX_COMMON_CLK
>  	bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
> @@ -102,3 +103,10 @@ config TESLA_FSD_COMMON_CLK
>  	help
>  	  Support for the clock controller present on the Tesla FSD SoC.
>  	  Choose Y here only if you build for this SoC.
> +
> +config ARTPEC8_COMMON_CLK

here, place it before EXYNOS_3250_COMMON_CLK.

> +	bool "Axis ARTPEC-8 clock controller support" if COMPILE_TEST
> +	depends on COMMON_CLK_SAMSUNG
> +	help



Best regards,
Krzysztof

Re: [PATCH 04/16] clk: samsung: artpec-8: Add initial clock support

[Hakyeong Kim]

On Thu, 2025-07-10 at 09:12 +0200, Krzysztof Kozlowski wrote:
> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> > From: Hakyeong Kim <hgkim05@coasia.com>
> > 
> > Add initial clock support for ARTPEC-8 SoC which is required
> > for enabling basic clock management.
> > 
> > Add clock support for below CMU block in ARTPEC-8 SoC:
> >  - CMU_IMEM
> > 
> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> > Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
> > ---
> >  drivers/clk/samsung/Kconfig       |  8 ++++
> >  drivers/clk/samsung/Makefile      |  1 +
> >  drivers/clk/samsung/clk-artpec8.c | 62
> > +++++++++++++++++++++++++++++++
> >  3 files changed, 71 insertions(+)
> >  create mode 100644 drivers/clk/samsung/clk-artpec8.c
> > 
> > diff --git a/drivers/clk/samsung/Kconfig
> > b/drivers/clk/samsung/Kconfig
> > index 76a494e95027..289591b403ad 100644
> > --- a/drivers/clk/samsung/Kconfig
> > +++ b/drivers/clk/samsung/Kconfig
> > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG
> >         select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
> >         select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
> >         select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
> > +       select ARTPEC8_COMMON_CLK if ARM64 && ARCH_ARTPEC8
> 
> Here and:
> 
> >  
> >  config S3C64XX_COMMON_CLK
> >         bool "Samsung S3C64xx clock controller support" if
> > COMPILE_TEST
> > @@ -102,3 +103,10 @@ config TESLA_FSD_COMMON_CLK
> >         help
> >           Support for the clock controller present on the Tesla FSD
> > SoC.
> >           Choose Y here only if you build for this SoC.
> > +
> > +config ARTPEC8_COMMON_CLK
> 
> here, place it before EXYNOS_3250_COMMON_CLK.

Ok, I will reorder macros in alphabatical order.

Thanks,
Hakyeong Kim

> 
> > +       bool "Axis ARTPEC-8 clock controller support" if
> > COMPILE_TEST
> > +       depends on COMMON_CLK_SAMSUNG
> > +       help
> 
> 
> 
> Best regards,
> Krzysztof

[PATCH 05/16] clk: samsung: artpec-8: Add clock support for CMU_CMU block

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add clock support for below CMU block in ARTPEC-8 SoC.
 - CMU_CMU

Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 drivers/clk/samsung/clk-artpec8.c | 415 ++++++++++++++++++++++++++++++
 1 file changed, 415 insertions(+)

diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c
index 11a48b2fcc09..1ef9e52ad24b 100644
--- a/drivers/clk/samsung/clk-artpec8.c
+++ b/drivers/clk/samsung/clk-artpec8.c
@@ -14,8 +14,423 @@
 #include "clk.h"
 
 /* NOTE: Must be equal to the last clock ID increased by one */
+#define CMU_CMU_NR_CLK			(DOUT_CLKCMU_VPP_CORE + 1)
 #define CMU_IMEM_NR_CLK			(MOUT_IMEM_JPEG_USER + 1)
 
+/* register offset definitions for cmu_cmu (0x12400000) */
+#define PLL_LOCKTIME_PLL_AUDIO			0x0000
+#define PLL_LOCKTIME_PLL_SHARED0		0x0004
+#define PLL_LOCKTIME_PLL_SHARED1		0x0008
+#define PLL_CON0_PLL_AUDIO			0x0100
+#define PLL_CON0_PLL_SHARED0			0x0120
+#define PLL_CON0_PLL_SHARED1			0x0140
+#define MUX_CLKCMU_2D				0x1000
+#define MUX_CLKCMU_3D				0x1004
+#define MUX_CLKCMU_BUS_BUS			0x1008
+#define MUX_CLKCMU_BUS_DLP			0x100c
+#define MUX_CLKCMU_CDC_CORE			0x1010
+#define MUX_CLKCMU_FSYS_SCAN0			0x1014
+#define MUX_CLKCMU_FSYS_SCAN1			0x1018
+#define MUX_CLKCMU_IMEM_JPEG			0x101c
+#define MUX_CLKCMU_PERI_DISP			0x1020
+#define MUX_CLKCMU_CORE_BUS			0x1024
+#define MUX_CLKCMU_CORE_DLP			0x1028
+#define MUX_CLKCMU_CPUCL_SWITCH			0x1030
+#define MUX_CLKCMU_DLP_CORE			0x1034
+#define MUX_CLKCMU_FSYS_BUS			0x1038
+#define MUX_CLKCMU_FSYS_IP			0x103c
+#define MUX_CLKCMU_IMEM_ACLK			0x1054
+#define MUX_CLKCMU_MIF_BUSP			0x1080
+#define MUX_CLKCMU_MIF_SWITCH			0x1084
+#define MUX_CLKCMU_PERI_IP			0x1088
+#define MUX_CLKCMU_RSP_CORE			0x108c
+#define MUX_CLKCMU_TRFM_CORE			0x1090
+#define MUX_CLKCMU_VCA_ACE			0x1094
+#define MUX_CLKCMU_VCA_OD			0x1098
+#define MUX_CLKCMU_VIO_CORE			0x109c
+#define MUX_CLKCMU_VIP0_CORE			0x10a0
+#define MUX_CLKCMU_VIP1_CORE			0x10a4
+#define MUX_CLKCMU_VPP_CORE			0x10a8
+
+#define DIV_CLKCMU_BUS_BUS			0x1800
+#define DIV_CLKCMU_BUS_DLP			0x1804
+#define DIV_CLKCMU_CDC_CORE			0x1808
+#define DIV_CLKCMU_FSYS_SCAN0			0x180c
+#define DIV_CLKCMU_FSYS_SCAN1			0x1810
+#define DIV_CLKCMU_IMEM_JPEG			0x1814
+#define DIV_CLKCMU_MIF_SWITCH			0x1818
+#define DIV_CLKCMU_CORE_DLP			0x181c
+#define DIV_CLKCMU_CORE_MAIN			0x1820
+#define DIV_CLKCMU_PERI_DISP			0x1824
+#define DIV_CLKCMU_CPUCL_SWITCH			0x1828
+#define DIV_CLKCMU_DLP_CORE			0x182c
+#define DIV_CLKCMU_FSYS_BUS			0x1830
+#define DIV_CLKCMU_FSYS_IP			0x1834
+#define DIV_CLKCMU_VIO_AUDIO			0x1838
+#define DIV_CLKCMU_GPU_2D			0x1848
+#define DIV_CLKCMU_GPU_3D			0x184c
+#define DIV_CLKCMU_IMEM_ACLK			0x1854
+#define DIV_CLKCMU_MIF_BUSP			0x1884
+#define DIV_CLKCMU_PERI_AUDIO			0x1890
+#define DIV_CLKCMU_PERI_IP			0x1894
+#define DIV_CLKCMU_RSP_CORE			0x1898
+#define DIV_CLKCMU_TRFM_CORE			0x189c
+#define DIV_CLKCMU_VCA_ACE			0x18a0
+#define DIV_CLKCMU_VCA_OD			0x18a4
+#define DIV_CLKCMU_VIO_CORE			0x18ac
+#define DIV_CLKCMU_VIP0_CORE			0x18b0
+#define DIV_CLKCMU_VIP1_CORE			0x18b4
+#define DIV_CLKCMU_VPP_CORE			0x18b8
+#define DIV_PLL_SHARED0_DIV2			0x18bc
+#define DIV_PLL_SHARED0_DIV3			0x18c0
+#define DIV_PLL_SHARED0_DIV4			0x18c4
+#define DIV_PLL_SHARED1_DIV2			0x18c8
+#define DIV_PLL_SHARED1_DIV3			0x18cc
+#define DIV_PLL_SHARED1_DIV4			0x18d0
+
+static const unsigned long cmu_cmu_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_AUDIO,
+	PLL_LOCKTIME_PLL_SHARED0,
+	PLL_LOCKTIME_PLL_SHARED1,
+	PLL_CON0_PLL_AUDIO,
+	PLL_CON0_PLL_SHARED0,
+	PLL_CON0_PLL_SHARED1,
+	MUX_CLKCMU_2D,
+	MUX_CLKCMU_3D,
+	MUX_CLKCMU_BUS_BUS,
+	MUX_CLKCMU_BUS_DLP,
+	MUX_CLKCMU_CDC_CORE,
+	MUX_CLKCMU_FSYS_SCAN0,
+	MUX_CLKCMU_FSYS_SCAN1,
+	MUX_CLKCMU_IMEM_JPEG,
+	MUX_CLKCMU_PERI_DISP,
+	MUX_CLKCMU_CORE_BUS,
+	MUX_CLKCMU_CORE_DLP,
+	MUX_CLKCMU_CPUCL_SWITCH,
+	MUX_CLKCMU_DLP_CORE,
+	MUX_CLKCMU_FSYS_BUS,
+	MUX_CLKCMU_FSYS_IP,
+	MUX_CLKCMU_IMEM_ACLK,
+	MUX_CLKCMU_MIF_BUSP,
+	MUX_CLKCMU_MIF_SWITCH,
+	MUX_CLKCMU_PERI_IP,
+	MUX_CLKCMU_RSP_CORE,
+	MUX_CLKCMU_TRFM_CORE,
+	MUX_CLKCMU_VCA_ACE,
+	MUX_CLKCMU_VCA_OD,
+	MUX_CLKCMU_VIO_CORE,
+	MUX_CLKCMU_VIP0_CORE,
+	MUX_CLKCMU_VIP1_CORE,
+	MUX_CLKCMU_VPP_CORE,
+	DIV_CLKCMU_BUS_BUS,
+	DIV_CLKCMU_BUS_DLP,
+	DIV_CLKCMU_CDC_CORE,
+	DIV_CLKCMU_FSYS_SCAN0,
+	DIV_CLKCMU_FSYS_SCAN1,
+	DIV_CLKCMU_IMEM_JPEG,
+	DIV_CLKCMU_MIF_SWITCH,
+	DIV_CLKCMU_CORE_DLP,
+	DIV_CLKCMU_CORE_MAIN,
+	DIV_CLKCMU_PERI_DISP,
+	DIV_CLKCMU_CPUCL_SWITCH,
+	DIV_CLKCMU_DLP_CORE,
+	DIV_CLKCMU_FSYS_BUS,
+	DIV_CLKCMU_FSYS_IP,
+	DIV_CLKCMU_VIO_AUDIO,
+	DIV_CLKCMU_GPU_2D,
+	DIV_CLKCMU_GPU_3D,
+	DIV_CLKCMU_IMEM_ACLK,
+	DIV_CLKCMU_MIF_BUSP,
+	DIV_CLKCMU_PERI_AUDIO,
+	DIV_CLKCMU_PERI_IP,
+	DIV_CLKCMU_RSP_CORE,
+	DIV_CLKCMU_TRFM_CORE,
+	DIV_CLKCMU_VCA_ACE,
+	DIV_CLKCMU_VCA_OD,
+	DIV_CLKCMU_VIO_CORE,
+	DIV_CLKCMU_VIP0_CORE,
+	DIV_CLKCMU_VIP1_CORE,
+	DIV_CLKCMU_VPP_CORE,
+	DIV_PLL_SHARED0_DIV2,
+	DIV_PLL_SHARED0_DIV3,
+	DIV_PLL_SHARED0_DIV4,
+	DIV_PLL_SHARED1_DIV2,
+	DIV_PLL_SHARED1_DIV3,
+	DIV_PLL_SHARED1_DIV4,
+};
+
+static const struct samsung_pll_rate_table artpec8_pll_audio_rates[] = {
+	PLL_36XX_RATE(25 * MHZ, 589823913U, 47, 1, 1, 12184),
+	PLL_36XX_RATE(25 * MHZ, 393215942U, 47, 3, 0, 12184),
+	PLL_36XX_RATE(25 * MHZ, 294911956U, 47, 1, 2, 12184),
+	PLL_36XX_RATE(25 * MHZ, 100000000U, 32, 2, 2, 0),
+	PLL_36XX_RATE(25 * MHZ,  98303985U, 47, 3, 2, 12184),
+	PLL_36XX_RATE(25 * MHZ,  49151992U, 47, 3, 3, 12184),
+};
+
+static const struct samsung_pll_clock cmu_cmu_pll_clks[] __initconst = {
+	PLL(pll_1017x, PLL_SHARED0, "fout_pll_shared0", "fin_pll",
+	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL),
+	PLL(pll_1017x, PLL_SHARED1, "fout_pll_shared1", "fin_pll",
+	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, NULL),
+	PLL(pll_1031x, PLL_AUDIO, "fout_pll_audio", "fin_pll",
+	    PLL_LOCKTIME_PLL_AUDIO, PLL_CON0_PLL_AUDIO, artpec8_pll_audio_rates),
+};
+
+PNAME(mout_clkcmu_bus_bus_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_bus_dlp_p) = {
+	"dout_pll_shared0_div2", "dout_pll_shared0_div4",
+	"dout_pll_shared1_div2", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_core_bus_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared0_div4", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_core_dlp_p) = {
+	"dout_pll_shared0_div2", "dout_pll_sahred1_div2",
+	"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_cpucl_switch_p) = {
+	"dout_pll_shared0_div2", "dout_pll_shared1_div2",
+	"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_fsys_bus_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div2",
+	"dout_pll_shared1_div4", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_fsys_ip_p) = {
+	"dout_pll_shared0_div2", "dout_pll_shared1_div3",
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3" };
+PNAME(mout_clkcmu_fsys_sfmc_p) = {
+	"dout_pll_shared1_div3", "dout_pll_shared0_div2",
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3" };
+PNAME(mout_clkcmu_fsys_scan0_p) = {
+	"dout_pll_shared0_div4", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_fsys_scan1_p) = {
+	"dout_pll_shared0_div4", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_imem_imem_p) = {
+	"dout_pll_shared1_div4", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div2" };
+PNAME(mout_clkcmu_imem_jpeg_p) = {
+	"dout_pll_shared0_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div2", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_cdc_core_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_dlp_core_p) = {
+	"dout_pll_shared0_div2", "dout_pll_shared1_div2",
+	"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_3d_p) = {
+	"dout_pll_shared0_div2", "dout_pll_shared1_div2",
+	"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_2d_p) = {
+	"dout_pll_shared0_div2", "dout_pll_shared1_div2",
+	"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_mif_switch_p) = {
+	"dout_pll_shared0", "dout_pll_shared1",
+	"dout_pll_shared0_div2", "dout_pll_shared0_div3" };
+PNAME(mout_clkcmu_mif_busp_p) = {
+	"dout_pll_shared0_div3", "dout_pll_shared1_div4",
+	"dout_pll_shared0_div4", "dout_pll_shared0_div2" };
+PNAME(mout_clkcmu_peri_disp_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div2",
+	"dout_pll_shared1_div4", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_peri_ip_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div4",
+	"dout_pll_shared1_div4", "dout_pll_shared0_div2" };
+PNAME(mout_clkcmu_rsp_core_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_trfm_core_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vca_ace_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vca_od_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vio_core_p) = {
+	"dout_pll_shared0_div3", "dout_pll_shared0_div2",
+	"dout_pll_shared1_div2", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_vip0_core_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vip1_core_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vpp_core_p) = {
+	"dout_pll_shared1_div2", "dout_pll_shared0_div3",
+	"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_pll_shared0_p) = { "fin_pll", "fout_pll_shared0" };
+PNAME(mout_clkcmu_pll_shared1_p) = { "fin_pll", "fout_pll_shared1" };
+PNAME(mout_clkcmu_pll_audio_p) = { "fin_pll", "fout_pll_audio" };
+
+static const struct samsung_fixed_factor_clock cmu_fixed_factor_clks[] __initconst = {
+	FFACTOR(DOUT_CLKCMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0),
+};
+
+static const struct samsung_mux_clock cmu_cmu_mux_clks[] __initconst = {
+	MUX(0, "mout_clkcmu_pll_shared0", mout_clkcmu_pll_shared0_p,
+	    PLL_CON0_PLL_SHARED0, 4, 1),
+	MUX(0, "mout_clkcmu_pll_shared1", mout_clkcmu_pll_shared1_p,
+	    PLL_CON0_PLL_SHARED1, 4, 1),
+	MUX(0, "mout_clkcmu_pll_audio", mout_clkcmu_pll_audio_p,
+	    PLL_CON0_PLL_AUDIO, 4, 1),
+	MUX(0, "mout_clkcmu_bus_bus", mout_clkcmu_bus_bus_p,
+	    MUX_CLKCMU_BUS_BUS, 0, 2),
+	MUX(0, "mout_clkcmu_bus_dlp", mout_clkcmu_bus_dlp_p,
+	    MUX_CLKCMU_BUS_DLP, 0, 2),
+	MUX(0, "mout_clkcmu_core_bus", mout_clkcmu_core_bus_p,
+	    MUX_CLKCMU_CORE_BUS, 0, 2),
+	MUX(0, "mout_clkcmu_core_dlp", mout_clkcmu_core_dlp_p,
+	    MUX_CLKCMU_CORE_DLP, 0, 2),
+	MUX(0, "mout_clkcmu_cpucl_switch", mout_clkcmu_cpucl_switch_p,
+	    MUX_CLKCMU_CPUCL_SWITCH, 0, 3),
+	MUX(0, "mout_clkcmu_fsys_bus", mout_clkcmu_fsys_bus_p,
+	    MUX_CLKCMU_FSYS_BUS, 0, 2),
+	MUX(0, "mout_clkcmu_fsys_ip", mout_clkcmu_fsys_ip_p,
+	    MUX_CLKCMU_FSYS_IP, 0, 2),
+	MUX(0, "mout_clkcmu_fsys_scan0", mout_clkcmu_fsys_scan0_p,
+	    MUX_CLKCMU_FSYS_SCAN0, 0, 1),
+	MUX(0, "mout_clkcmu_fsys_scan1", mout_clkcmu_fsys_scan1_p,
+	    MUX_CLKCMU_FSYS_SCAN1, 0, 1),
+	MUX(0, "mout_clkcmu_imem_imem", mout_clkcmu_imem_imem_p,
+	    MUX_CLKCMU_IMEM_ACLK, 0, 2),
+	MUX(0, "mout_clkcmu_imem_jpeg", mout_clkcmu_imem_jpeg_p,
+	    MUX_CLKCMU_IMEM_JPEG, 0, 2),
+	nMUX(0, "mout_clkcmu_cdc_core", mout_clkcmu_cdc_core_p,
+	     MUX_CLKCMU_CDC_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_dlp_core", mout_clkcmu_dlp_core_p,
+	     MUX_CLKCMU_DLP_CORE, 0, 2),
+	MUX(0, "mout_clkcmu_3d", mout_clkcmu_3d_p,
+	    MUX_CLKCMU_3D, 0, 2),
+	MUX(0, "mout_clkcmu_2d", mout_clkcmu_2d_p,
+	    MUX_CLKCMU_2D, 0, 2),
+	MUX(0, "mout_clkcmu_mif_switch", mout_clkcmu_mif_switch_p,
+	    MUX_CLKCMU_MIF_SWITCH, 0, 2),
+	MUX(0, "mout_clkcmu_mif_busp", mout_clkcmu_mif_busp_p,
+	    MUX_CLKCMU_MIF_BUSP, 0, 2),
+	MUX(0, "mout_clkcmu_peri_disp", mout_clkcmu_peri_disp_p,
+	    MUX_CLKCMU_PERI_DISP, 0, 2),
+	MUX(0, "mout_clkcmu_peri_ip", mout_clkcmu_peri_ip_p,
+	    MUX_CLKCMU_PERI_IP, 0, 2),
+	MUX(0, "mout_clkcmu_rsp_core", mout_clkcmu_rsp_core_p,
+	    MUX_CLKCMU_RSP_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_trfm_core", mout_clkcmu_trfm_core_p,
+	     MUX_CLKCMU_TRFM_CORE, 0, 2),
+	MUX(0, "mout_clkcmu_vca_ace", mout_clkcmu_vca_ace_p,
+	    MUX_CLKCMU_VCA_ACE, 0, 2),
+	MUX(0, "mout_clkcmu_vca_od", mout_clkcmu_vca_od_p,
+	    MUX_CLKCMU_VCA_OD, 0, 2),
+	MUX(0, "mout_clkcmu_vio_core", mout_clkcmu_vio_core_p,
+	    MUX_CLKCMU_VIO_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_vip0_core", mout_clkcmu_vip0_core_p,
+	     MUX_CLKCMU_VIP0_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_vip1_core", mout_clkcmu_vip1_core_p,
+	     MUX_CLKCMU_VIP1_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_vpp_core", mout_clkcmu_vpp_core_p,
+	     MUX_CLKCMU_VPP_CORE, 0, 2),
+};
+
+static const struct samsung_div_clock cmu_cmu_div_clks[] __initconst = {
+	DIV(DOUT_PLL_SHARED0_DIV2, "dout_pll_shared0_div2",
+	    "mout_clkcmu_pll_shared0", DIV_PLL_SHARED0_DIV2, 0, 1),
+	DIV(DOUT_PLL_SHARED0_DIV3, "dout_pll_shared0_div3",
+	    "mout_clkcmu_pll_shared0", DIV_PLL_SHARED0_DIV3, 0, 2),
+	DIV(DOUT_PLL_SHARED0_DIV4, "dout_pll_shared0_div4",
+	    "dout_pll_shared0_div2", DIV_PLL_SHARED0_DIV4, 0, 1),
+	DIV(DOUT_PLL_SHARED1_DIV2, "dout_pll_shared1_div2",
+	    "mout_clkcmu_pll_shared1", DIV_PLL_SHARED1_DIV2, 0, 1),
+	DIV(DOUT_PLL_SHARED1_DIV3, "dout_pll_shared1_div3",
+	    "mout_clkcmu_pll_shared1", DIV_PLL_SHARED1_DIV3, 0, 2),
+	DIV(DOUT_PLL_SHARED1_DIV4, "dout_pll_shared1_div4",
+	    "dout_pll_shared1_div2", DIV_PLL_SHARED1_DIV4, 0, 1),
+	DIV(DOUT_CLKCMU_BUS_BUS, "dout_clkcmu_bus_bus",
+	    "mout_clkcmu_bus_bus", DIV_CLKCMU_BUS_BUS, 0, 4),
+	DIV(DOUT_CLKCMU_BUS_DLP, "dout_clkcmu_bus_dlp",
+	    "mout_clkcmu_bus_dlp", DIV_CLKCMU_BUS_DLP, 0, 4),
+	DIV(DOUT_CLKCMU_CORE_MAIN, "dout_clkcmu_core_main",
+	    "mout_clkcmu_core_bus", DIV_CLKCMU_CORE_MAIN, 0, 4),
+	DIV(DOUT_CLKCMU_CORE_DLP, "dout_clkcmu_core_dlp",
+	    "mout_clkcmu_core_dlp", DIV_CLKCMU_CORE_DLP, 0, 4),
+	DIV(DOUT_CLKCMU_CPUCL_SWITCH, "dout_clkcmu_cpucl_switch",
+	    "mout_clkcmu_cpucl_switch", DIV_CLKCMU_CPUCL_SWITCH, 0, 3),
+	DIV(DOUT_CLKCMU_FSYS_BUS, "dout_clkcmu_fsys_bus",
+	    "mout_clkcmu_fsys_bus", DIV_CLKCMU_FSYS_BUS, 0, 4),
+	DIV(DOUT_CLKCMU_FSYS_IP, "dout_clkcmu_fsys_ip",
+	    "mout_clkcmu_fsys_ip", DIV_CLKCMU_FSYS_IP, 0, 9),
+	DIV(DOUT_CLKCMU_FSYS_SCAN0, "dout_clkcmu_fsys_scan0",
+	    "mout_clkcmu_fsys_scan0", DIV_CLKCMU_FSYS_SCAN0, 0, 4),
+	DIV(DOUT_CLKCMU_FSYS_SCAN1, "dout_clkcmu_fsys_scan1",
+	    "mout_clkcmu_fsys_scan1", DIV_CLKCMU_FSYS_SCAN1, 0, 4),
+	DIV(DOUT_CLKCMU_IMEM_ACLK, "dout_clkcmu_imem_aclk",
+	    "mout_clkcmu_imem_imem", DIV_CLKCMU_IMEM_ACLK, 0, 4),
+	DIV(DOUT_CLKCMU_IMEM_JPEG, "dout_clkcmu_imem_jpeg",
+	    "mout_clkcmu_imem_jpeg", DIV_CLKCMU_IMEM_JPEG, 0, 4),
+	DIV_F(DOUT_CLKCMU_CDC_CORE, "dout_clkcmu_cdc_core",
+	      "mout_clkcmu_cdc_core", DIV_CLKCMU_CDC_CORE, 0, 4,
+	      CLK_SET_RATE_PARENT, 0),
+	DIV_F(DOUT_CLKCMU_DLP_CORE, "dout_clkcmu_dlp_core",
+	      "mout_clkcmu_dlp_core", DIV_CLKCMU_DLP_CORE, 0, 4,
+	      CLK_SET_RATE_PARENT, 0),
+	DIV(DOUT_CLKCMU_GPU_3D, "dout_clkcmu_gpu_3d",
+	    "mout_clkcmu_3d", DIV_CLKCMU_GPU_3D, 0, 3),
+	DIV(DOUT_CLKCMU_GPU_2D, "dout_clkcmu_gpu_2d",
+	    "mout_clkcmu_2d", DIV_CLKCMU_GPU_2D, 0, 4),
+	DIV(DOUT_CLKCMU_MIF_SWITCH, "dout_clkcmu_mif_switch",
+	    "mout_clkcmu_mif_switch", DIV_CLKCMU_MIF_SWITCH, 0, 4),
+	DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp",
+	    "mout_clkcmu_mif_busp", DIV_CLKCMU_MIF_BUSP, 0, 3),
+	DIV(DOUT_CLKCMU_PERI_DISP, "dout_clkcmu_peri_disp",
+	    "mout_clkcmu_peri_disp", DIV_CLKCMU_PERI_DISP, 0, 4),
+	DIV(DOUT_CLKCMU_PERI_IP, "dout_clkcmu_peri_ip",
+	    "mout_clkcmu_peri_ip", DIV_CLKCMU_PERI_IP, 0, 4),
+	DIV(DOUT_CLKCMU_PERI_AUDIO, "dout_clkcmu_peri_audio",
+	    "mout_clkcmu_pll_audio", DIV_CLKCMU_PERI_AUDIO, 0, 4),
+	DIV(DOUT_CLKCMU_RSP_CORE, "dout_clkcmu_rsp_core",
+	    "mout_clkcmu_rsp_core", DIV_CLKCMU_RSP_CORE, 0, 4),
+	DIV_F(DOUT_CLKCMU_TRFM_CORE, "dout_clkcmu_trfm_core",
+	      "mout_clkcmu_trfm_core", DIV_CLKCMU_TRFM_CORE, 0, 4,
+	      CLK_SET_RATE_PARENT, 0),
+	DIV(DOUT_CLKCMU_VCA_ACE, "dout_clkcmu_vca_ace",
+	    "mout_clkcmu_vca_ace", DIV_CLKCMU_VCA_ACE, 0, 4),
+	DIV(DOUT_CLKCMU_VCA_OD, "dout_clkcmu_vca_od",
+	    "mout_clkcmu_vca_od", DIV_CLKCMU_VCA_OD, 0, 4),
+	DIV(DOUT_CLKCMU_VIO_CORE, "dout_clkcmu_vio_core",
+	    "mout_clkcmu_vio_core", DIV_CLKCMU_VIO_CORE, 0, 4),
+	DIV(DOUT_CLKCMU_VIO_AUDIO, "dout_clkcmu_vio_audio",
+	    "mout_clkcmu_pll_audio", DIV_CLKCMU_VIO_AUDIO, 0, 4),
+	DIV_F(DOUT_CLKCMU_VIP0_CORE, "dout_clkcmu_vip0_core",
+	      "mout_clkcmu_vip0_core", DIV_CLKCMU_VIP0_CORE, 0, 4,
+	      CLK_SET_RATE_PARENT, 0),
+	DIV_F(DOUT_CLKCMU_VIP1_CORE, "dout_clkcmu_vip1_core",
+	      "mout_clkcmu_vip1_core", DIV_CLKCMU_VIP1_CORE, 0, 4,
+	      CLK_SET_RATE_PARENT, 0),
+	DIV_F(DOUT_CLKCMU_VPP_CORE, "dout_clkcmu_vpp_core",
+	      "mout_clkcmu_vpp_core", DIV_CLKCMU_VPP_CORE, 0, 4,
+	      CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info cmu_cmu_info __initconst = {
+	.pll_clks		= cmu_cmu_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(cmu_cmu_pll_clks),
+	.fixed_factor_clks	= cmu_fixed_factor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(cmu_fixed_factor_clks),
+	.mux_clks		= cmu_cmu_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_cmu_mux_clks),
+	.div_clks		= cmu_cmu_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_cmu_div_clks),
+	.nr_clk_ids		= CMU_CMU_NR_CLK,
+	.clk_regs		= cmu_cmu_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_cmu_clk_regs),
+};
+
+static void __init artpec8_clk_cmu_cmu_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &cmu_cmu_info);
+}
+
+CLK_OF_DECLARE(artpec8_clk_cmu_cmu, "axis,artpec8-cmu-cmu",
+	       artpec8_clk_cmu_cmu_init);
+
 /* Register Offset definitions for CMU_IMEM (0x10010000) */
 #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER			0x0100
 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER			0x0120
-- 
2.34.1

[PATCH 06/16] clk: samsung: artpec-8: Add clock support for CMU_BUS block

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add clock support for below CMU block in ARTPEC-8 SoC.
 - CMU_BUS

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 drivers/clk/samsung/clk-artpec8.c | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c
index 1ef9e52ad24b..648abdd2f510 100644
--- a/drivers/clk/samsung/clk-artpec8.c
+++ b/drivers/clk/samsung/clk-artpec8.c
@@ -15,6 +15,7 @@
 
 /* NOTE: Must be equal to the last clock ID increased by one */
 #define CMU_CMU_NR_CLK			(DOUT_CLKCMU_VPP_CORE + 1)
+#define CMU_BUS_NR_CLK			(DOUT_CLK_BUS_PCLK + 1)
 #define CMU_IMEM_NR_CLK			(MOUT_IMEM_JPEG_USER + 1)
 
 /* register offset definitions for cmu_cmu (0x12400000) */
@@ -431,6 +432,50 @@ static void __init artpec8_clk_cmu_cmu_init(struct device_node *np)
 CLK_OF_DECLARE(artpec8_clk_cmu_cmu, "axis,artpec8-cmu-cmu",
 	       artpec8_clk_cmu_cmu_init);
 
+/* Register Offset definitions for CMU_BUS (0x12c10000) */
+#define PLL_CON0_MUX_CLK_BUS_ACLK_USER			0x0100
+#define PLL_CON0_MUX_CLK_BUS_DLP_USER			0x0120
+#define DIV_CLK_BUS_PCLK				0x1800
+
+static const unsigned long cmu_bus_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLK_BUS_ACLK_USER,
+	PLL_CON0_MUX_CLK_BUS_DLP_USER,
+	DIV_CLK_BUS_PCLK,
+};
+
+PNAME(mout_clk_bus_aclk_user_p) = { "fin_pll", "dout_clkcmu_bus_bus" };
+PNAME(mout_clk_bus_dlp_user_p) = { "fin_pll", "dout_clkcmu_bus_dlp" };
+
+static const struct samsung_mux_clock cmu_bus_mux_clks[] __initconst = {
+	MUX(MOUT_CLK_BUS_ACLK_USER, "mout_clk_bus_aclk_user",
+	    mout_clk_bus_aclk_user_p, PLL_CON0_MUX_CLK_BUS_ACLK_USER, 4, 1),
+	MUX(MOUT_CLK_BUS_DLP_USER, "mout_clk_bus_dlp_user",
+	    mout_clk_bus_dlp_user_p, PLL_CON0_MUX_CLK_BUS_DLP_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_bus_div_clks[] __initconst = {
+	DIV(DOUT_CLK_BUS_PCLK, "dout_clk_bus_pclk", "mout_clk_bus_aclk_user",
+	    DIV_CLK_BUS_PCLK, 0, 4),
+};
+
+static const struct samsung_cmu_info cmu_bus_info __initconst = {
+	.mux_clks		= cmu_bus_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_bus_mux_clks),
+	.div_clks		= cmu_bus_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_bus_div_clks),
+	.nr_clk_ids		= CMU_BUS_NR_CLK,
+	.clk_regs		= cmu_bus_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_bus_clk_regs),
+};
+
+static void __init artpec8_clk_cmu_bus_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &cmu_bus_info);
+}
+
+CLK_OF_DECLARE(artpec8_clk_cmu_bus, "axis,artpec8-cmu-bus",
+	       artpec8_clk_cmu_bus_init);
+
 /* Register Offset definitions for CMU_IMEM (0x10010000) */
 #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER			0x0100
 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER			0x0120
-- 
2.34.1

[PATCH 07/16] clk: samsung: artpec-8: Add clock support for CMU_CORE block

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add clock support for below CMU block in ARTPEC-8 SoC.
 - CMU_CORE

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 drivers/clk/samsung/clk-artpec8.c | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c
index 648abdd2f510..f41b7941c630 100644
--- a/drivers/clk/samsung/clk-artpec8.c
+++ b/drivers/clk/samsung/clk-artpec8.c
@@ -16,6 +16,7 @@
 /* NOTE: Must be equal to the last clock ID increased by one */
 #define CMU_CMU_NR_CLK			(DOUT_CLKCMU_VPP_CORE + 1)
 #define CMU_BUS_NR_CLK			(DOUT_CLK_BUS_PCLK + 1)
+#define CMU_CORE_NR_CLK			(DOUT_CLK_CORE_PCLK + 1)
 #define CMU_IMEM_NR_CLK			(MOUT_IMEM_JPEG_USER + 1)
 
 /* register offset definitions for cmu_cmu (0x12400000) */
@@ -476,6 +477,50 @@ static void __init artpec8_clk_cmu_bus_init(struct device_node *np)
 CLK_OF_DECLARE(artpec8_clk_cmu_bus, "axis,artpec8-cmu-bus",
 	       artpec8_clk_cmu_bus_init);
 
+/* Register Offset definitions for CMU_CORE (0x12410000) */
+#define PLL_CON0_MUX_CLK_CORE_ACLK_USER			0x0100
+#define PLL_CON0_MUX_CLK_CORE_DLP_USER			0x0120
+#define DIV_CLK_CORE_PCLK				0x1800
+
+static const unsigned long cmu_core_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLK_CORE_ACLK_USER,
+	PLL_CON0_MUX_CLK_CORE_DLP_USER,
+	DIV_CLK_CORE_PCLK,
+};
+
+PNAME(mout_clk_core_aclk_user_p) = { "fin_pll", "dout_clkcmu_core_main" };
+PNAME(mout_clk_core_dlp_user_p) = { "fin_pll", "dout_clkcmu_core_dlp" };
+
+static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst = {
+	MUX(MOUT_CLK_CORE_ACLK_USER, "mout_clk_core_aclk_user",
+	    mout_clk_core_aclk_user_p, PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1),
+	MUX(MOUT_CLK_CORE_DLP_USER, "mout_clk_core_dlp_user",
+	    mout_clk_core_dlp_user_p, PLL_CON0_MUX_CLK_CORE_DLP_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_core_div_clks[] __initconst = {
+	DIV(DOUT_CLK_CORE_PCLK, "dout_clk_core_pclk",
+	    "mout_clk_core_aclk_user", DIV_CLK_CORE_PCLK, 0, 4),
+};
+
+static const struct samsung_cmu_info cmu_core_info __initconst = {
+	.mux_clks		= cmu_core_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_core_mux_clks),
+	.div_clks		= cmu_core_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_core_div_clks),
+	.nr_clk_ids		= CMU_CORE_NR_CLK,
+	.clk_regs		= cmu_core_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_core_clk_regs),
+};
+
+static void __init artpec8_clk_cmu_core_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &cmu_core_info);
+}
+
+CLK_OF_DECLARE(artpec8_clk_cmu_core, "axis,artpec8-cmu-core",
+	       artpec8_clk_cmu_core_init);
+
 /* Register Offset definitions for CMU_IMEM (0x10010000) */
 #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER			0x0100
 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER			0x0120
-- 
2.34.1

[PATCH 08/16] clk: samsung: artpec-8: Add clock support for CMU_CPUCL block

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add clock support for below CMU block in ARTPEC-8 SoC.
 - CMU_CPUCL

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 drivers/clk/samsung/clk-artpec8.c | 99 +++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c
index f41b7941c630..15c90fe29308 100644
--- a/drivers/clk/samsung/clk-artpec8.c
+++ b/drivers/clk/samsung/clk-artpec8.c
@@ -17,6 +17,7 @@
 #define CMU_CMU_NR_CLK			(DOUT_CLKCMU_VPP_CORE + 1)
 #define CMU_BUS_NR_CLK			(DOUT_CLK_BUS_PCLK + 1)
 #define CMU_CORE_NR_CLK			(DOUT_CLK_CORE_PCLK + 1)
+#define CMU_CPUCL_NR_CLK		(DOUT_CLK_CPUCL_PCLKDBG + 1)
 #define CMU_IMEM_NR_CLK			(MOUT_IMEM_JPEG_USER + 1)
 
 /* register offset definitions for cmu_cmu (0x12400000) */
@@ -521,6 +522,104 @@ static void __init artpec8_clk_cmu_core_init(struct device_node *np)
 CLK_OF_DECLARE(artpec8_clk_cmu_core, "axis,artpec8-cmu-core",
 	       artpec8_clk_cmu_core_init);
 
+/* Register Offset definitions for CMU_CPUCL (0x11410000) */
+#define PLL_LOCKTIME_PLL_CPUCL				0x0000
+#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER		0x0120
+#define PLL_CON0_PLL_CPUCL				0x0140
+#define MUX_CLK_CPUCL_PLL				0x1000
+#define DIV_CLK_CLUSTER_ACLK				0x1800
+#define DIV_CLK_CLUSTER_CNTCLK				0x1804
+#define DIV_CLK_CLUSTER_PCLKDBG				0x1808
+#define DIV_CLK_CPUCL_CMUREF				0x180c
+#define DIV_CLK_CPUCL_PCLK				0x1814
+#define DIV_CLK_CLUSTER_ATCLK				0x1818
+#define DIV_CLK_CPUCL_DBG				0x181c
+#define DIV_CLK_CPUCL_PCLKDBG				0x1820
+
+static const unsigned long cmu_cpucl_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_CPUCL,
+	PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER,
+	PLL_CON0_PLL_CPUCL,
+	MUX_CLK_CPUCL_PLL,
+	DIV_CLK_CLUSTER_ACLK,
+	DIV_CLK_CLUSTER_CNTCLK,
+	DIV_CLK_CLUSTER_PCLKDBG,
+	DIV_CLK_CPUCL_CMUREF,
+	DIV_CLK_CPUCL_PCLK,
+	DIV_CLK_CLUSTER_ATCLK,
+	DIV_CLK_CPUCL_DBG,
+	DIV_CLK_CPUCL_PCLKDBG,
+};
+
+static const struct samsung_pll_clock cmu_cpucl_pll_clks[] __initconst = {
+	PLL(pll_1017x, PLL_CPUCL, "fout_pll_cpucl", "fin_pll",
+	    PLL_LOCKTIME_PLL_CPUCL, PLL_CON0_PLL_CPUCL, NULL),
+};
+
+PNAME(mout_clkcmu_cpucl_switch_user_p) = {
+	"fin_pll", "dout_clkcmu_cpucl_switch" };
+PNAME(mout_pll_cpucl_p) = {
+	"fin_pll", "fout_pll_cpucl" };
+PNAME(mout_clk_cpucl_pll_p) = {
+	"mout_pll_cpucl", "mout_clkcmu_cpucl_switch_user" };
+
+static const struct samsung_mux_clock cmu_cpucl_mux_clks[] __initconst = {
+	MUX_F(0, "mout_pll_cpucl", mout_pll_cpucl_p,
+	      PLL_CON0_PLL_CPUCL, 4, 1,
+	      CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
+	MUX(MOUT_CLKCMU_CPUCL_SWITCH_USER, "mout_clkcmu_cpucl_switch_user",
+	    mout_clkcmu_cpucl_switch_user_p,
+	    PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, 4, 1),
+	MUX_F(MOUT_CLK_CPUCL_PLL, "mout_clk_cpucl_pll", mout_clk_cpucl_pll_p,
+	      MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_fixed_factor_clock cpucl_ffactor_clks[] __initconst = {
+	FFACTOR(DOUT_CLK_CPUCL_CPU, "dout_clk_cpucl_cpu",
+		"mout_clk_cpucl_pll", 1, 1, CLK_SET_RATE_PARENT),
+};
+
+static const struct samsung_div_clock cmu_cpucl_div_clks[] __initconst = {
+	DIV(DOUT_CLK_CLUSTER_ACLK, "dout_clk_cluster_aclk",
+	    "dout_clk_cpucl_cpu", DIV_CLK_CLUSTER_ACLK, 0, 4),
+	DIV(DOUT_CLK_CLUSTER_PCLKDBG, "dout_clk_cluster_pclkdbg",
+	    "dout_clk_cpucl_cpu", DIV_CLK_CLUSTER_PCLKDBG, 0, 4),
+	DIV(DOUT_CLK_CLUSTER_CNTCLK, "dout_clk_cluster_cntclk",
+	    "dout_clk_cpucl_cpu", DIV_CLK_CLUSTER_CNTCLK, 0, 4),
+	DIV(DOUT_CLK_CLUSTER_ATCLK, "dout_clk_cluster_atclk",
+	    "dout_clk_cpucl_cpu", DIV_CLK_CLUSTER_ATCLK, 0, 4),
+	DIV(DOUT_CLK_CPUCL_PCLK, "dout_clk_cpucl_pclk",
+	    "dout_clk_cpucl_cpu", DIV_CLK_CPUCL_PCLK, 0, 4),
+	DIV(DOUT_CLK_CPUCL_CMUREF, "dout_clk_cpucl_cmuref",
+	    "dout_clk_cpucl_cpu", DIV_CLK_CPUCL_CMUREF, 0, 3),
+	DIV(DOUT_CLK_CPUCL_DBG, "dout_clk_cpucl_dbg",
+	    "dout_clk_cpucl_cpu", DIV_CLK_CPUCL_DBG, 0, 4),
+	DIV(DOUT_CLK_CPUCL_PCLKDBG, "dout_clk_cpucl_pclkdbg",
+	    "dout_clk_cpucl_dbg", DIV_CLK_CPUCL_PCLKDBG, 0, 4),
+};
+
+static const struct samsung_cmu_info cmu_cpucl_info __initconst = {
+	.pll_clks		= cmu_cpucl_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(cmu_cpucl_pll_clks),
+	.fixed_factor_clks	= cpucl_ffactor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(cpucl_ffactor_clks),
+	.mux_clks		= cmu_cpucl_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_cpucl_mux_clks),
+	.div_clks		= cmu_cpucl_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_cpucl_div_clks),
+	.nr_clk_ids		= CMU_CPUCL_NR_CLK,
+	.clk_regs		= cmu_cpucl_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_cpucl_clk_regs),
+};
+
+static void __init artpec8_clk_cmu_cpucl_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &cmu_cpucl_info);
+}
+
+CLK_OF_DECLARE(artpec8_clk_cmu_cpucl, "axis,artpec8-cmu-cpucl",
+	       artpec8_clk_cmu_cpucl_init);
+
 /* Register Offset definitions for CMU_IMEM (0x10010000) */
 #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER			0x0100
 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER			0x0120
-- 
2.34.1

[PATCH 09/16] clk: samsung: artpec-8: Add clock support for CMU_FSYS block

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add clock support for below CMU block in ARTPEC-8 SoC.
 - CMU_FSYS

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 drivers/clk/samsung/clk-artpec8.c | 134 ++++++++++++++++++++++++++++++
 1 file changed, 134 insertions(+)

diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c
index 15c90fe29308..7ccec4ff8f70 100644
--- a/drivers/clk/samsung/clk-artpec8.c
+++ b/drivers/clk/samsung/clk-artpec8.c
@@ -18,6 +18,7 @@
 #define CMU_BUS_NR_CLK			(DOUT_CLK_BUS_PCLK + 1)
 #define CMU_CORE_NR_CLK			(DOUT_CLK_CORE_PCLK + 1)
 #define CMU_CPUCL_NR_CLK		(DOUT_CLK_CPUCL_PCLKDBG + 1)
+#define CMU_FSYS_NR_CLK			(DOUT_SCAN_CLK_FSYS_MMC + 1)
 #define CMU_IMEM_NR_CLK			(MOUT_IMEM_JPEG_USER + 1)
 
 /* register offset definitions for cmu_cmu (0x12400000) */
@@ -620,6 +621,139 @@ static void __init artpec8_clk_cmu_cpucl_init(struct device_node *np)
 CLK_OF_DECLARE(artpec8_clk_cmu_cpucl, "axis,artpec8-cmu-cpucl",
 	       artpec8_clk_cmu_cpucl_init);
 
+/* Register Offset definitions for CMU_FSYS (0x16c10000) */
+#define PLL_LOCKTIME_PLL_FSYS				0x0004
+#define PLL_CON0_MUX_CLK_FSYS_BUS_USER			0x0120
+#define PLL_CON0_MUX_CLK_FSYS_MMC_USER			0x0140
+#define PLL_CON0_MUX_CLK_FSYS_SCAN0_USER		0x0160
+#define PLL_CON0_MUX_CLK_FSYS_SCAN1_USER		0x0180
+#define PLL_CON0_PLL_FSYS				0x01c0
+#define DIV_CLK_FSYS_ADC				0x1804
+#define DIV_CLK_FSYS_BUS300				0x1808
+#define DIV_CLK_FSYS_BUS_QSPI				0x180c
+#define DIV_CLK_FSYS_EQOS_25				0x1810
+#define DIV_CLK_FSYS_EQOS_2P5				0x1814
+#define DIV_CLK_FSYS_EQOS_500				0x1818
+#define DIV_CLK_FSYS_EQOS_INT125			0x181c
+#define DIV_CLK_FSYS_MMC_CARD0				0x1820
+#define DIV_CLK_FSYS_MMC_CARD1				0x1824
+#define DIV_CLK_FSYS_OTP_MEM				0x1828
+#define DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL		0x182c
+#define DIV_CLK_FSYS_QSPI				0x1830
+#define DIV_CLK_FSYS_SCLK_UART				0x1834
+#define DIV_CLK_FSYS_SFMC_NAND				0x1838
+#define DIV_SCAN_CLK_FSYS_125				0x183c
+#define DIV_SCAN_CLK_FSYS_MMC				0x1840
+#define DIV_SCAN_CLK_FSYS_PCIE_PIPE			0x1844
+
+static const unsigned long cmu_fsys_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_FSYS,
+	PLL_CON0_MUX_CLK_FSYS_BUS_USER,
+	PLL_CON0_MUX_CLK_FSYS_MMC_USER,
+	PLL_CON0_MUX_CLK_FSYS_SCAN0_USER,
+	PLL_CON0_MUX_CLK_FSYS_SCAN1_USER,
+	PLL_CON0_PLL_FSYS,
+	DIV_CLK_FSYS_ADC,
+	DIV_CLK_FSYS_BUS300,
+	DIV_CLK_FSYS_BUS_QSPI,
+	DIV_CLK_FSYS_EQOS_25,
+	DIV_CLK_FSYS_EQOS_2P5,
+	DIV_CLK_FSYS_EQOS_500,
+	DIV_CLK_FSYS_EQOS_INT125,
+	DIV_CLK_FSYS_MMC_CARD0,
+	DIV_CLK_FSYS_MMC_CARD1,
+	DIV_CLK_FSYS_OTP_MEM,
+	DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL,
+	DIV_CLK_FSYS_QSPI,
+	DIV_CLK_FSYS_SCLK_UART,
+	DIV_CLK_FSYS_SFMC_NAND,
+	DIV_SCAN_CLK_FSYS_125,
+	DIV_SCAN_CLK_FSYS_MMC,
+	DIV_SCAN_CLK_FSYS_PCIE_PIPE,
+};
+
+static const struct samsung_pll_clock cmu_fsys_pll_clks[] __initconst = {
+	PLL(pll_1017x, PLL_FSYS, "fout_pll_fsys", "fin_pll",
+	    PLL_LOCKTIME_PLL_FSYS, PLL_CON0_PLL_FSYS, NULL),
+};
+
+PNAME(mout_fsys_scan0_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan0" };
+PNAME(mout_fsys_scan1_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan1" };
+PNAME(mout_fsys_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys_bus" };
+PNAME(mout_fsys_mmc_user_p) = { "fin_pll", "dout_clkcmu_fsys_ip" };
+PNAME(mout_fsys_pll_fsys_p) = { "fin_pll", "fout_pll_fsys" };
+
+static const struct samsung_mux_clock cmu_fsys_mux_clks[] __initconst = {
+	MUX(0, "mout_clk_pll_fsys", mout_fsys_pll_fsys_p, PLL_CON0_PLL_FSYS, 4, 1),
+	MUX(MOUT_FSYS_SCAN0_USER, "mout_fsys_scan0_user",
+	    mout_fsys_scan0_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN0_USER, 4, 1),
+	MUX(MOUT_FSYS_SCAN1_USER, "mout_fsys_scan1_user",
+	    mout_fsys_scan1_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN1_USER, 4, 1),
+	MUX(MOUT_FSYS_BUS_USER, "mout_fsys_bus_user",
+	    mout_fsys_bus_user_p, PLL_CON0_MUX_CLK_FSYS_BUS_USER, 4, 1),
+	MUX(MOUT_FSYS_MMC_USER, "mout_fsys_mmc_user",
+	    mout_fsys_mmc_user_p, PLL_CON0_MUX_CLK_FSYS_MMC_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_fsys_div_clks[] __initconst = {
+	DIV(DOUT_FSYS_PCIE_PIPE, "dout_fsys_pcie_pipe", "mout_clk_pll_fsys",
+	    DIV_SCAN_CLK_FSYS_PCIE_PIPE, 0, 4),
+	DIV(DOUT_FSYS_ADC, "dout_fsys_adc", "mout_clk_pll_fsys",
+	    DIV_CLK_FSYS_ADC, 0, 7),
+	DIV(DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL,
+	    "dout_fsys_pcie_phy_refclk_syspll", "mout_clk_pll_fsys",
+	    DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, 0, 8),
+	DIV(DOUT_FSYS_QSPI, "dout_fsys_qspi", "mout_fsys_mmc_user",
+	    DIV_CLK_FSYS_QSPI, 0, 4),
+	DIV(DOUT_FSYS_EQOS_INT125, "dout_fsys_eqos_int125", "mout_clk_pll_fsys",
+	    DIV_CLK_FSYS_EQOS_INT125, 0, 4),
+	DIV(DOUT_FSYS_OTP_MEM, "dout_fsys_otp_mem", "fin_pll",
+	    DIV_CLK_FSYS_OTP_MEM, 0, 9),
+	DIV(DOUT_FSYS_SCLK_UART, "dout_fsys_sclk_uart", "mout_clk_pll_fsys",
+	    DIV_CLK_FSYS_SCLK_UART, 0, 10),
+	DIV(DOUT_FSYS_SFMC_NAND, "dout_fsys_sfmc_nand", "mout_fsys_mmc_user",
+	    DIV_CLK_FSYS_SFMC_NAND, 0, 4),
+	DIV(DOUT_SCAN_CLK_FSYS_125,
+	    "dout_scan_clk_fsys_125", "mout_clk_pll_fsys",
+	    DIV_SCAN_CLK_FSYS_125, 0, 4),
+	DIV(DOUT_SCAN_CLK_FSYS_MMC, "dout_scan_clk_fsys_mmc", "fout_pll_fsys",
+	    DIV_SCAN_CLK_FSYS_MMC, 0, 4),
+	DIV(DOUT_FSYS_EQOS_25, "dout_fsys_eqos_25", "dout_fsys_eqos_int125",
+	    DIV_CLK_FSYS_EQOS_25, 0, 4),
+	DIV_F(DOUT_FSYS_EQOS_2p5, "dout_fsys_eqos_2p5", "dout_fsys_eqos_25",
+	      DIV_CLK_FSYS_EQOS_2P5, 0, 4, CLK_SET_RATE_PARENT, 0),
+	DIV(0, "dout_fsys_eqos_500", "mout_clk_pll_fsys",
+	    DIV_CLK_FSYS_EQOS_500, 0, 4),
+	DIV(DOUT_FSYS_BUS300, "dout_fsys_bus300", "mout_fsys_bus_user",
+	    DIV_CLK_FSYS_BUS300, 0, 4),
+	DIV(DOUT_FSYS_BUS_QSPI, "dout_fsys_bus_qspi", "mout_fsys_mmc_user",
+	    DIV_CLK_FSYS_BUS_QSPI, 0, 4),
+	DIV(DOUT_FSYS_MMC_CARD0, "dout_fsys_mmc_card0", "mout_fsys_mmc_user",
+	    DIV_CLK_FSYS_MMC_CARD0, 0, 10),
+	DIV(DOUT_FSYS_MMC_CARD1, "dout_fsys_mmc_card1", "mout_fsys_mmc_user",
+	    DIV_CLK_FSYS_MMC_CARD1, 0, 10),
+};
+
+static const struct samsung_cmu_info cmu_fsys_info __initconst = {
+	.pll_clks		= cmu_fsys_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(cmu_fsys_pll_clks),
+	.mux_clks		= cmu_fsys_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_fsys_mux_clks),
+	.div_clks		= cmu_fsys_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_fsys_div_clks),
+	.nr_clk_ids		= CMU_FSYS_NR_CLK,
+	.clk_regs		= cmu_fsys_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_fsys_clk_regs),
+};
+
+static void __init artpec8_clk_cmu_fsys_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &cmu_fsys_info);
+}
+
+CLK_OF_DECLARE(artpec8_clk_cmu_fsys, "axis,artpec8-cmu-fsys",
+	       artpec8_clk_cmu_fsys_init);
+
 /* Register Offset definitions for CMU_IMEM (0x10010000) */
 #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER			0x0100
 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER			0x0120
-- 
2.34.1

[PATCH 10/16] clk: samsung: artpec-8: Add clock support for CMU_PERI block

[ksk4725]

From: Hakyeong Kim <hgkim05@coasia.com>

Add clock support for below CMU block in ARTPEC-8 SoC.
 - CMU_PERI

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
---
 drivers/clk/samsung/clk-artpec8.c | 90 +++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c
index 7ccec4ff8f70..f45bc9c113f0 100644
--- a/drivers/clk/samsung/clk-artpec8.c
+++ b/drivers/clk/samsung/clk-artpec8.c
@@ -20,6 +20,7 @@
 #define CMU_CPUCL_NR_CLK		(DOUT_CLK_CPUCL_PCLKDBG + 1)
 #define CMU_FSYS_NR_CLK			(DOUT_SCAN_CLK_FSYS_MMC + 1)
 #define CMU_IMEM_NR_CLK			(MOUT_IMEM_JPEG_USER + 1)
+#define CMU_PERI_NR_CLK			(DOUT_PERI_DSIM + 1)
 
 /* register offset definitions for cmu_cmu (0x12400000) */
 #define PLL_LOCKTIME_PLL_AUDIO			0x0000
@@ -798,3 +799,92 @@ static void __init artpec8_clk_cmu_imem_init(struct device_node *np)
 
 CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem",
 	       artpec8_clk_cmu_imem_init);
+
+/* Register Offset definitions for CMU_PERI (0x16410000) */
+#define PLL_CON0_MUX_CLK_PERI_AUDIO_USER		0x0100
+#define PLL_CON0_MUX_CLK_PERI_DISP_USER			0x0120
+#define PLL_CON0_MUX_CLK_PERI_IP_USER			0x0140
+#define MUX_CLK_PERI_I2S0				0x1000
+#define MUX_CLK_PERI_I2S1				0x1004
+#define DIV_CLK_PERI_DSIM				0x1800
+#define DIV_CLK_PERI_I2S0				0x1804
+#define DIV_CLK_PERI_I2S1				0x1808
+#define DIV_CLK_PERI_PCLK				0x180c
+#define DIV_CLK_PERI_SPI				0x1810
+#define DIV_CLK_PERI_UART1				0x1814
+#define DIV_CLK_PERI_UART2				0x1818
+
+static const unsigned long cmu_peri_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLK_PERI_AUDIO_USER,
+	PLL_CON0_MUX_CLK_PERI_DISP_USER,
+	PLL_CON0_MUX_CLK_PERI_IP_USER,
+	MUX_CLK_PERI_I2S0,
+	MUX_CLK_PERI_I2S1,
+	DIV_CLK_PERI_DSIM,
+	DIV_CLK_PERI_I2S0,
+	DIV_CLK_PERI_I2S1,
+	DIV_CLK_PERI_PCLK,
+	DIV_CLK_PERI_SPI,
+	DIV_CLK_PERI_UART1,
+	DIV_CLK_PERI_UART2,
+};
+
+static const struct samsung_fixed_rate_clock peri_fixed_clks[] __initconst = {
+	FRATE(0, "clk_peri_audio", NULL, 0, 100000000),
+};
+
+PNAME(mout_peri_ip_user_p) = { "fin_pll", "dout_clkcmu_peri_ip" };
+PNAME(mout_peri_audio_user_p) = { "fin_pll", "dout_clkcmu_peri_audio" };
+PNAME(mout_peri_disp_user_p) = { "fin_pll", "dout_clkcmu_peri_disp" };
+PNAME(mout_peri_i2s0_p) = { "dout_peri_i2s0", "clk_peri_audio" };
+PNAME(mout_peri_i2s1_p) = { "dout_peri_i2s1", "clk_peri_audio" };
+
+static const struct samsung_mux_clock cmu_peri_mux_clks[] __initconst = {
+	MUX(MOUT_PERI_IP_USER, "mout_peri_ip_user", mout_peri_ip_user_p,
+	    PLL_CON0_MUX_CLK_PERI_IP_USER, 4, 1),
+	MUX(MOUT_PERI_AUDIO_USER, "mout_peri_audio_user",
+	    mout_peri_audio_user_p, PLL_CON0_MUX_CLK_PERI_AUDIO_USER, 4, 1),
+	MUX(MOUT_PERI_DISP_USER, "mout_peri_disp_user", mout_peri_disp_user_p,
+	    PLL_CON0_MUX_CLK_PERI_DISP_USER, 4, 1),
+	MUX(MOUT_PERI_I2S0, "mout_peri_i2s0", mout_peri_i2s0_p,
+	    MUX_CLK_PERI_I2S0, 0, 1),
+	MUX(MOUT_PERI_I2S1, "mout_peri_i2s1", mout_peri_i2s1_p,
+	    MUX_CLK_PERI_I2S1, 0, 1),
+};
+
+static const struct samsung_div_clock cmu_peri_div_clks[] __initconst = {
+	DIV(DOUT_PERI_SPI, "dout_peri_spi", "mout_peri_ip_user",
+	    DIV_CLK_PERI_SPI, 0, 10),
+	DIV(DOUT_PERI_UART1, "dout_peri_uart1", "mout_peri_ip_user",
+	    DIV_CLK_PERI_UART1, 0, 10),
+	DIV(DOUT_PERI_UART2, "dout_peri_uart2", "mout_peri_ip_user",
+	    DIV_CLK_PERI_UART2, 0, 10),
+	DIV(DOUT_PERI_PCLK, "dout_peri_pclk", "mout_peri_ip_user",
+	    DIV_CLK_PERI_PCLK, 0, 4),
+	DIV(DOUT_PERI_I2S0, "dout_peri_i2s0", "mout_peri_audio_user",
+	    DIV_CLK_PERI_I2S0, 0, 4),
+	DIV(DOUT_PERI_I2S1, "dout_peri_i2s1", "mout_peri_audio_user",
+	    DIV_CLK_PERI_I2S1, 0, 4),
+	DIV(DOUT_PERI_DSIM, "dout_peri_dsim", "mout_peri_disp_user",
+	    DIV_CLK_PERI_DSIM, 0, 4),
+};
+
+static const struct samsung_cmu_info cmu_peri_info __initconst = {
+	.mux_clks		= cmu_peri_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_peri_mux_clks),
+	.div_clks		= cmu_peri_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_peri_div_clks),
+	.fixed_clks		= peri_fixed_clks,
+	.nr_fixed_clks		= ARRAY_SIZE(peri_fixed_clks),
+	.nr_clk_ids		= CMU_PERI_NR_CLK,
+	.clk_regs		= cmu_peri_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_peri_clk_regs),
+};
+
+static void __init artpec8_clk_cmu_peri_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &cmu_peri_info);
+}
+
+CLK_OF_DECLARE(artpec8_clk_cmu_peri, "axis,artpec8-cmu-peri",
+	       artpec8_clk_cmu_peri_init);
-- 
2.34.1

Re: [PATCH 10/16] clk: samsung: artpec-8: Add clock support for CMU_PERI block

[Krzysztof Kozlowski]

On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> From: Hakyeong Kim <hgkim05@coasia.com>
> 
> Add clock support for below CMU block in ARTPEC-8 SoC.
>  - CMU_PERI
> 
> Signed-off-by: Varada Pavani <v.pavani@samsung.com>
> Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
> ---
>  drivers/clk/samsung/clk-artpec8.c | 90 +++++++++++++++++++++++++++++++
>  1 file changed, 90 insertions(+)

Please squash all the clock driver patches.

Best regards,
Krzysztof

Re: [PATCH 10/16] clk: samsung: artpec-8: Add clock support for CMU_PERI block

[Hakyeong Kim]

On Thu, 2025-07-10 at 09:13 +0200, Krzysztof Kozlowski wrote:
> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> > From: Hakyeong Kim <hgkim05@coasia.com>
> > 
> > Add clock support for below CMU block in ARTPEC-8 SoC.
> >  - CMU_PERI
> > 
> > Signed-off-by: Varada Pavani <v.pavani@samsung.com>
> > Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
> > ---
> >  drivers/clk/samsung/clk-artpec8.c | 90
> > +++++++++++++++++++++++++++++++
> >  1 file changed, 90 insertions(+)
> 
> Please squash all the clock driver patches.

My intention here is to split the clock changes so as to make smaller
patches.
I will squash patch 04 to 10 and make a single clock driver patch.

Thanks,
Hakyeong Kim

> 
> Best regards,
> Krzysztof

[PATCH 11/16] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC

[ksk4725]

From: SeonGu Kang <ksk4725@coasia.com>

Document the compatible string for ARTPEC-8 SoC pinctrl block,
which is similar to other Samsung SoC pinctrl blocks.

Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
---
 Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index de8460856141..9386dcd418c2 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -35,6 +35,7 @@ properties:
 
   compatible:
     enum:
+      - axis,artpec8-pinctrl
       - google,gs101-pinctrl
       - samsung,s3c2412-pinctrl
       - samsung,s3c2416-pinctrl
-- 
2.34.1

[PATCH 12/16] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration

[ksk4725]

From: SeonGu Kang <ksk4725@coasia.com>

Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl.
It is similar to other Samsung SoC pinctrl blocks.

Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
---
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 50 +++++++++++++++++++
 drivers/pinctrl/samsung/pinctrl-exynos.h      | 10 ++++
 drivers/pinctrl/samsung/pinctrl-samsung.c     |  2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |  1 +
 4 files changed, 63 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index dd07720e32cc..ee3b488b00ff 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -76,6 +76,15 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off  = {
 	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
 };
 
+/*
+ * Bank type for non-alive type. Bit fields:
+ * CON: 4, DAT: 1, PUD: 4, DRV: 4
+ */
+static const struct samsung_pin_bank_type artpec_bank_type_off = {
+	.fld_width = { 4, 1, 4, 4, },
+	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
 /* Pad retention control code for accessing PMU regmap */
 static atomic_t exynos_shared_retention_refcnt;
 
@@ -1814,3 +1823,44 @@ const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
 	.ctrl		= gs101_pin_ctrl,
 	.num_ctrl	= ARRAY_SIZE(gs101_pin_ctrl),
 };
+
+/* pin banks of artpec8 pin-controller (FSYS0) */
+static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = {
+	ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00),
+	ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04),
+	ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08),
+	ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c),
+	ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10),
+	ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14),
+	ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18),
+	ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c),
+	ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20),
+	ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24),
+};
+
+/* pin banks of artpec8 pin-controller (PERIC) */
+static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = {
+	ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+	ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04),
+	ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+	ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c),
+};
+
+static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = {
+	{
+		/* pin-controller instance 0 FSYS data */
+		.pin_banks	= artpec8_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(artpec8_pin_banks0),
+		.eint_gpio_init	= exynos_eint_gpio_init,
+	}, {
+		/* pin-controller instance 1 PERIC data */
+		.pin_banks	= artpec8_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(artpec8_pin_banks1),
+		.eint_gpio_init	= exynos_eint_gpio_init,
+	},
+};
+
+const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = {
+	.ctrl		= artpec8_pin_ctrl,
+	.num_ctrl	= ARRAY_SIZE(artpec8_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index b483270ddc53..6bc04cb5ac9f 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -216,6 +216,16 @@
 		.name			= id				\
 	}
 
+#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs)			\
+	{								\
+		.type			= &artpec_bank_type_off,	\
+		.pctl_offset		= reg,				\
+		.nr_pins		= pins,				\
+		.eint_type		= EINT_TYPE_GPIO,		\
+		.eint_offset		= offs,				\
+		.name			= id				\
+	}
+
 /**
  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
  * generated by the external wakeup interrupt controller.
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 2896eb2de2c0..993efba5a9ad 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1468,6 +1468,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
 		.data = &s5pv210_of_data },
 #endif
 #ifdef CONFIG_PINCTRL_EXYNOS_ARM64
+	{ .compatible = "axis,artpec8-pinctrl",
+		.data = &artpec8_of_data },
 	{ .compatible = "google,gs101-pinctrl",
 		.data = &gs101_of_data },
 	{ .compatible = "samsung,exynos2200-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 3cf758df7d69..bfd88ad2f3ff 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -377,6 +377,7 @@ struct samsung_pmx_func {
 };
 
 /* list of all exported SoC specific data */
+extern const struct samsung_pinctrl_of_match_data artpec8_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
-- 
2.34.1

[PATCH 13/16] dt-bindings: arm: Add Axis ARTPEC SoC platform

[ksk4725]

From: Ravi Patel <ravi.patel@samsung.com>

Add device tree bindings for the Axis ARTPEC-8 SoC platform
and ARTPEC-8 Grizzly board.

Also move the existing ARTPEC-6 related bindings from .txt
to yaml format.

Signed-off-by: sungminpark <smn1196@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 .../devicetree/bindings/arm/axis.txt          | 13 -------
 .../devicetree/bindings/arm/axis.yaml         | 35 +++++++++++++++++++
 2 files changed, 35 insertions(+), 13 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt
 create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml

diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt
deleted file mode 100644
index ebd33a88776f..000000000000
--- a/Documentation/devicetree/bindings/arm/axis.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Axis Communications AB
-ARTPEC series SoC Device Tree Bindings
-
-ARTPEC-6 ARM SoC
-================
-
-Required root node properties:
-- compatible = "axis,artpec6";
-
-ARTPEC-6 Development board:
----------------------------
-Required root node properties:
-- compatible = "axis,artpec6-dev-board", "axis,artpec6";
diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml
new file mode 100644
index 000000000000..70fb3caa70df
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/axis.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/axis.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axis ARTPEC platforms
+
+maintainers:
+  - Jesper Nilsson <jesper.nilsson@axis.com>
+  - SeonGu Kang <ksk4725@coasia.com>
+  - SungMin Park <smn1196@coasia.com>
+  - Ravi Patel <ravi.patel@samsung.com>
+  - linux-arm-kernel@axis.com
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Axis ARTPEC-6 Development board
+        items:
+          - enum:
+              - axis,artpec6-dev-board
+          - const: axis,artpec6
+
+      - description: Axis ARTPEC-8 Grizzly board
+        items:
+          - enum:
+              - axis,artpec8-grizzly
+          - const: axis,artpec8
+
+additionalProperties: true
+
+...
-- 
2.34.1

Re: [PATCH 13/16] dt-bindings: arm: Add Axis ARTPEC SoC platform

[Krzysztof Kozlowski]

On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> From: Ravi Patel <ravi.patel@samsung.com>
> 
> Add device tree bindings for the Axis ARTPEC-8 SoC platform
> and ARTPEC-8 Grizzly board.
> 
> Also move the existing ARTPEC-6 related bindings from .txt
> to yaml format.

Don't mix conversion with new boards.

> 
> Signed-off-by: sungminpark <smn1196@coasia.com>
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>

Same problems about SoB chain...

> ---



Best regards,
Krzysztof

Re: [PATCH 13/16] dt-bindings: arm: Add Axis ARTPEC SoC platform

[sungmin]

2025-07-10 (목), 09:15 +0200, Krzysztof Kozlowski:
> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> > From: Ravi Patel <ravi.patel@samsung.com>
> > 
> > Add device tree bindings for the Axis ARTPEC-8 SoC platform
> > and ARTPEC-8 Grizzly board.
> > 
> > Also move the existing ARTPEC-6 related bindings from .txt
> > to yaml format.
> 
> Don't mix conversion with new boards.
The original intention for conversion here is to satisfy the dt-
bindings check warnings.
I will break this patch into 2 patches where 1st will be conversion
from txt to yaml and 2nd will be adding new board.
> 
> > 
> > Signed-off-by: sungminpark <smn1196@coasia.com>
> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> 
> Same problems about SoB chain...
Ok, I will update the SoB section in next patches.

Thanks,
sungminpark
> 
> > ---
> 
> 
> 
> Best regards,
> Krzysztof

[PATCH 14/16] arm64: dts: axis: Add initial device tree support

[ksk4725]

From: sungminpark <smn1196@coasia.com>

Add initial device tree support for Axis ARTPEC-8 SoC and Grizzly board.
This SoC contains four cores of cortex-a53 CPUs and other various
peripheral IPs.

Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Signed-off-by: sungminpark <smn1196@coasia.com>
---
 MAINTAINERS                                  |  14 ++
 arch/arm64/Kconfig.platforms                 |  13 +
 arch/arm64/boot/dts/Makefile                 |   1 +
 arch/arm64/boot/dts/axis/Makefile            |   4 +
 arch/arm64/boot/dts/axis/artpec8-grizzly.dts |  67 +++++
 arch/arm64/boot/dts/axis/artpec8.dtsi        | 252 +++++++++++++++++++
 6 files changed, 351 insertions(+)
 create mode 100644 arch/arm64/boot/dts/axis/Makefile
 create mode 100644 arch/arm64/boot/dts/axis/artpec8-grizzly.dts
 create mode 100644 arch/arm64/boot/dts/axis/artpec8.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index fa1e04e87d1d..371005f3f41a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2320,6 +2320,20 @@ F:	drivers/crypto/axis
 F:	drivers/mmc/host/usdhi6rol0.c
 F:	drivers/pinctrl/pinctrl-artpec*
 
+ARM/ARTPEC ARM64 MACHINE SUPPORT
+M:	Jesper Nilsson <jesper.nilsson@axis.com>
+M:	Ravi Patel <ravi.patel@samsung.com>
+M:	SeonGu Kang <ksk4725@coasia.com>
+M:	SungMin Park <smn1196@coasia.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	linux-samsung-soc@vger.kernel.org
+L:	linux-arm-kernel@axis.com
+S:	Maintained
+F:	Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml
+F:	arch/arm64/boot/dts/axis/
+F:	drivers/clk/samsung/clk-artpec*.c
+F:	include/dt-bindings/clock/axis,artpec*-clk.h
+
 ARM/ASPEED I2C DRIVER
 M:	Ryan Chen <ryan_chen@aspeedtech.com>
 R:	Benjamin Herrenschmidt <benh@kernel.crashing.org>
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 8b76821f190f..418ee47227c1 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -40,6 +40,19 @@ config ARCH_APPLE
 	  This enables support for Apple's in-house ARM SoC family, such
 	  as the Apple M1.
 
+config ARCH_ARTPEC
+	bool "Axis Communications ARTPEC SoC Family"
+	help
+	   This enables support for the ARMv8 based ARTPEC SoC Family.
+
+config ARCH_ARTPEC8
+	bool "Axis ARTPEC-8 SoC Platform"
+	depends on ARCH_ARTPEC
+	depends on ARCH_EXYNOS
+	select ARM_GIC
+	help
+	  This enables support for the Axis ARTPEC-8 SoC.
+
 menuconfig ARCH_BCM
 	bool "Broadcom SoC Support"
 
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc2..6b6a3aedc2ed 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += amlogic
 subdir-y += apm
 subdir-y += apple
 subdir-y += arm
+subdir-y += axis
 subdir-y += bitmain
 subdir-y += blaize
 subdir-y += broadcom
diff --git a/arch/arm64/boot/dts/axis/Makefile b/arch/arm64/boot/dts/axis/Makefile
new file mode 100644
index 000000000000..ccf00de64016
--- /dev/null
+++ b/arch/arm64/boot/dts/axis/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_ARTPEC) += \
+	artpec8-grizzly.dtb
diff --git a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
new file mode 100644
index 000000000000..7671130a0333
--- /dev/null
+++ b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Axis ARTPEC-8 Grizzly board device tree source
+ *
+ * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2022-2025  Axis Communications AB.
+ *             https://www.axis.com
+ */
+
+/dts-v1/;
+#include "artpec8.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
+	model = "ARTPEC-8 grizzly board";
+	compatible = "axis,artpec8-grizzly", "axis,artpec8";
+
+	aliases {
+		serial0 = &serial_0;
+	};
+
+	chosen {
+		stdout-path = &serial_0;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+};
+
+&osc_clk {
+	clock-frequency = <50000000>;
+	status = "okay";
+};
+
+&serial_0 {
+	status = "okay";
+};
+
+&cmu_cmu {
+	status = "okay";
+};
+
+&cmu_bus {
+	status = "okay";
+};
+
+&cmu_core {
+	status = "okay";
+};
+
+&cmu_cpucl {
+	status = "okay";
+};
+
+&cmu_fsys {
+	status = "okay";
+};
+
+&cmu_imem {
+	status = "okay";
+};
+
+&cmu_peri {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/axis/artpec8.dtsi b/arch/arm64/boot/dts/axis/artpec8.dtsi
new file mode 100644
index 000000000000..296192560adf
--- /dev/null
+++ b/arch/arm64/boot/dts/axis/artpec8.dtsi
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Axis ARTPEC-8 SoC device tree source
+ *
+ * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2022-2025  Axis Communications AB.
+ *             https://www.axis.com
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axis,artpec8-clk.h>
+
+/ {
+	compatible = "axis,artpec8";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			cpu-idle-states = <&cpu_sleep>;
+			enable-method = "psci";
+			clocks = <&cmu_cpucl DOUT_CLK_CPUCL_CPU>;
+			clock-names = "dout_clk_cpucl_cpu";
+			clock-frequency = <1200000000>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			cpu-idle-states = <&cpu_sleep>;
+			enable-method = "psci";
+			clock-frequency = <1200000000>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			cpu-idle-states = <&cpu_sleep>;
+			enable-method = "psci";
+			clock-frequency = <1200000000>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			cpu-idle-states = <&cpu_sleep>;
+			enable-method = "psci";
+			clock-frequency = <1200000000>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_sleep: cpu-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <300>;
+				exit-latency-us = <1200>;
+				min-residency-us = <2000>;
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	osc_clk: xxti {
+		compatible = "fixed-clock";
+		clock-output-names = "xxti";
+		#clock-cells = <0>;
+	};
+
+	fin_pll: fin_pll {
+		compatible = "fixed-factor-clock";
+		clocks = <&osc_clk>;
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clock-output-names = "fin_pll";
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x17000000>;
+
+		mct@10040000 {
+			compatible = "samsung,exynos4210-mct";
+			reg = <0x10040000 0x1000>;
+			clocks = <&fin_pll>, <&cmu_imem MOUT_IMEM_ACLK_USER>;
+			clock-names = "fin_pll", "mct";
+			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		gic: interrupt-controller@10201000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x10201000 0x00001000>,
+			      <0x10202000 0x00002000>,
+			      <0x10204000 0x00002000>,
+			      <0x10206000 0x00002000>;
+		};
+
+		cmu_cmu: clock-controller@12400000 {
+			compatible = "axis,artpec8-cmu-cmu";
+			reg = <0x12400000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>;
+			clock-names = "fin_pll";
+			status = "disabled";
+		};
+
+		cmu_bus: clock-controller@12c10000 {
+			compatible = "axis,artpec8-cmu-bus";
+			reg = <0x12c10000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu DOUT_CLKCMU_BUS_BUS>,
+				 <&cmu_cmu DOUT_CLKCMU_BUS_DLP>;
+			clock-names = "fin_pll",
+				      "dout_clkcmu_bus_bus",
+				      "dout_clkcmu_bus_dlp";
+			status = "disabled";
+		};
+
+		cmu_core: clock-controller@12410000 {
+			compatible = "axis,artpec8-cmu-core";
+			reg = <0x12410000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu DOUT_CLKCMU_CORE_MAIN>,
+				 <&cmu_cmu DOUT_CLKCMU_CORE_DLP>;
+			clock-names = "fin_pll",
+				      "dout_clkcmu_core_main",
+				      "dout_clkcmu_core_dlp";
+			status = "disabled";
+		};
+
+		cmu_cpucl: clock-controller@11410000 {
+			compatible = "axis,artpec8-cmu-cpucl";
+			reg = <0x11410000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu DOUT_CLKCMU_CPUCL_SWITCH>;
+			clock-names = "fin_pll",
+				"dout_clkcmu_cpucl_switch";
+			status = "disabled";
+		};
+
+		cmu_fsys: clock-controller@16c10000 {
+			compatible = "axis,artpec8-cmu-fsys";
+			reg = <0x16c10000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>,
+				 <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>,
+				 <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>,
+				 <&cmu_cmu DOUT_CLKCMU_FSYS_IP>;
+			clock-names = "fin_pll",
+				      "dout_clkcmu_fsys_scan0",
+				      "dout_clkcmu_fsys_scan1",
+				      "dout_clkcmu_fsys_bus",
+				      "dout_clkcmu_fsys_ip";
+			status = "disabled";
+		};
+
+		cmu_imem: clock-controller@10010000 {
+			compatible = "axis,artpec8-cmu-imem";
+			reg = <0x10010000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu DOUT_CLKCMU_IMEM_ACLK>,
+				 <&cmu_cmu DOUT_CLKCMU_IMEM_JPEG>;
+			clock-names = "fin_pll",
+				      "dout_clkcmu_imem_aclk",
+				      "dout_clkcmu_imem_jpeg";
+			status = "disabled";
+		};
+
+		cmu_peri: clock-controller@16410000 {
+			compatible = "axis,artpec8-cmu-peri";
+			reg = <0x16410000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu DOUT_CLKCMU_PERI_IP>,
+				 <&cmu_cmu DOUT_CLKCMU_PERI_AUDIO>,
+				 <&cmu_cmu DOUT_CLKCMU_PERI_DISP>;
+			clock-names = "fin_pll",
+				      "dout_clkcmu_peri_ip",
+				      "dout_clkcmu_peri_audio",
+				      "dout_clkcmu_peri_disp";
+			status = "disabled";
+		};
+
+		serial_0: serial@16cc0000 {
+			compatible = "axis,artpec8-uart";
+			reg = <0x16cc0000 0x100>;
+			clocks = <&cmu_fsys DOUT_FSYS_BUS300>,
+				 <&cmu_fsys DOUT_FSYS_SCLK_UART>;
+			clock-names = "uart", "clk_uart_baud0";
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&serial0_bus>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.34.1

Re: [PATCH 14/16] arm64: dts: axis: Add initial device tree support

[Krzysztof Kozlowski]

On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> From: sungminpark <smn1196@coasia.com>
> 
> Add initial device tree support for Axis ARTPEC-8 SoC and Grizzly board.
> This SoC contains four cores of cortex-a53 CPUs and other various

Subject: Initial device tree of what?

> peripheral IPs.
> 
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> Signed-off-by: sungminpark <smn1196@coasia.com>
> ---
>  MAINTAINERS                                  |  14 ++
>  arch/arm64/Kconfig.platforms                 |  13 +
>  arch/arm64/boot/dts/Makefile                 |   1 +
>  arch/arm64/boot/dts/axis/Makefile            |   4 +
>  arch/arm64/boot/dts/axis/artpec8-grizzly.dts |  67 +++++
>  arch/arm64/boot/dts/axis/artpec8.dtsi        | 252 +++++++++++++++++++
>  6 files changed, 351 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/axis/Makefile
>  create mode 100644 arch/arm64/boot/dts/axis/artpec8-grizzly.dts
>  create mode 100644 arch/arm64/boot/dts/axis/artpec8.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fa1e04e87d1d..371005f3f41a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2320,6 +2320,20 @@ F:	drivers/crypto/axis
>  F:	drivers/mmc/host/usdhi6rol0.c
>  F:	drivers/pinctrl/pinctrl-artpec*
>  
> +ARM/ARTPEC ARM64 MACHINE SUPPORT

This is samsung soc, so I need a pattern for that as well as I will be
handling patches.

> +M:	Jesper Nilsson <jesper.nilsson@axis.com>
> +M:	Ravi Patel <ravi.patel@samsung.com>
> +M:	SeonGu Kang <ksk4725@coasia.com>
> +M:	SungMin Park <smn1196@coasia.com>

Please keep only maintainers who will actually perform reviews of the
code. I am not even sure if this is worth separate entry outside of
Samsung. Please list the IP blocks which are not Samsung here.

> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +L:	linux-samsung-soc@vger.kernel.org
> +L:	linux-arm-kernel@axis.com
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml
> +F:	arch/arm64/boot/dts/axis/
> +F:	drivers/clk/samsung/clk-artpec*.c
> +F:	include/dt-bindings/clock/axis,artpec*-clk.h
> +
>  ARM/ASPEED I2C DRIVER
>  M:	Ryan Chen <ryan_chen@aspeedtech.com>
>  R:	Benjamin Herrenschmidt <benh@kernel.crashing.org>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 8b76821f190f..418ee47227c1 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -40,6 +40,19 @@ config ARCH_APPLE
>  	  This enables support for Apple's in-house ARM SoC family, such
>  	  as the Apple M1.
>  
> +config ARCH_ARTPEC
> +	bool "Axis Communications ARTPEC SoC Family"
> +	help
> +	   This enables support for the ARMv8 based ARTPEC SoC Family.
> +
> +config ARCH_ARTPEC8

No, drop. One ARCH symbol.

> +	bool "Axis ARTPEC-8 SoC Platform"
> +	depends on ARCH_ARTPEC
> +	depends on ARCH_EXYNOS

And that's the proof that this is Samsung SoC.

> +	select ARM_GIC
> +	help
> +	  This enables support for the Axis ARTPEC-8 SoC.
> +
>  menuconfig ARCH_BCM
>  	bool "Broadcom SoC Support"
>  
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc2..6b6a3aedc2ed 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += amlogic
>  subdir-y += apm
>  subdir-y += apple
>  subdir-y += arm
> +subdir-y += axis
>  subdir-y += bitmain
>  subdir-y += blaize
>  subdir-y += broadcom
> diff --git a/arch/arm64/boot/dts/axis/Makefile b/arch/arm64/boot/dts/axis/Makefile
> new file mode 100644
> index 000000000000..ccf00de64016
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axis/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_ARTPEC) += \
> +	artpec8-grizzly.dtb
> diff --git a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> new file mode 100644
> index 000000000000..7671130a0333
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Axis ARTPEC-8 Grizzly board device tree source
> + *
> + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> + *             https://www.samsung.com
> + * Copyright (c) 2022-2025  Axis Communications AB.
> + *             https://www.axis.com
> + */
> +
> +/dts-v1/;
> +#include "artpec8.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +/ {
> +	model = "ARTPEC-8 grizzly board";
> +	compatible = "axis,artpec8-grizzly", "axis,artpec8";
> +
> +	aliases {
> +		serial0 = &serial_0;
> +	};
> +
> +	chosen {
> +		stdout-path = &serial_0;
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x0 0x80000000>;
> +	};
> +};
> +
> +&osc_clk {
> +	clock-frequency = <50000000>;
> +	status = "okay";

Why?

> +};
> +
> +&serial_0 {

Follow DTS coding style. s > c
o > c


> +	status = "okay";
> +};
> +
> +&cmu_cmu {
> +	status = "okay";
> +};
> +
> +&cmu_bus {
> +	status = "okay";
> +};
> +
> +&cmu_core {
> +	status = "okay";
> +};
> +
> +&cmu_cpucl {
> +	status = "okay";
> +};
> +
> +&cmu_fsys {
> +	status = "okay";
> +};
> +
> +&cmu_imem {
> +	status = "okay";
> +};
> +
> +&cmu_peri {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/axis/artpec8.dtsi b/arch/arm64/boot/dts/axis/artpec8.dtsi
> new file mode 100644
> index 000000000000..296192560adf
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axis/artpec8.dtsi
> @@ -0,0 +1,252 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Axis ARTPEC-8 SoC device tree source
> + *
> + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> + *             https://www.samsung.com
> + * Copyright (c) 2022-2025  Axis Communications AB.
> + *             https://www.axis.com
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/axis,artpec8-clk.h>
> +
> +/ {
> +	compatible = "axis,artpec8";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0>;
> +			cpu-idle-states = <&cpu_sleep>;
> +			enable-method = "psci";
> +			clocks = <&cmu_cpucl DOUT_CLK_CPUCL_CPU>;
> +			clock-names = "dout_clk_cpucl_cpu";
> +			clock-frequency = <1200000000>;

This feels wrong. Frequency changes, doesn't it?

> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x1>;
> +			cpu-idle-states = <&cpu_sleep>;
> +			enable-method = "psci";
> +			clock-frequency = <1200000000>;
> +		};
> +
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x2>;
> +			cpu-idle-states = <&cpu_sleep>;
> +			enable-method = "psci";
> +			clock-frequency = <1200000000>;
> +		};
> +
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x3>;
> +			cpu-idle-states = <&cpu_sleep>;
> +			enable-method = "psci";
> +			clock-frequency = <1200000000>;
> +		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			cpu_sleep: cpu-sleep {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010000>;
> +				local-timer-stop;
> +				entry-latency-us = <300>;
> +				exit-latency-us = <1200>;
> +				min-residency-us = <2000>;
> +			};
> +		};
> +	};
> +
> +	timer {

Also wrongly ordered. See DTS coding style.


> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	osc_clk: xxti {

clock-xxti

> +		compatible = "fixed-clock";
> +		clock-output-names = "xxti";
> +		#clock-cells = <0>;
> +	};
> +
> +	fin_pll: fin_pll {

DTS coding style.

> +		compatible = "fixed-factor-clock";
> +		clocks = <&osc_clk>;
> +		#clock-cells = <0>;
> +		clock-div = <2>;
> +		clock-mult = <1>;
> +		clock-output-names = "fin_pll";
> +	};
> +
> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x0 0x0 0x17000000>;

DTS coding style.

> +
> +		mct@10040000 {

Look at other SoCs first

> +			compatible = "samsung,exynos4210-mct";

You just missed two years of development, right? Look at other SoCs.


> +			reg = <0x10040000 0x1000>;
> +			clocks = <&fin_pll>, <&cmu_imem MOUT_IMEM_ACLK_USER>;
> +			clock-names = "fin_pll", "mct";
> +			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		gic: interrupt-controller@10201000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			reg = <0x10201000 0x00001000>,
> +			      <0x10202000 0x00002000>,
> +			      <0x10204000 0x00002000>,
> +			      <0x10206000 0x00002000>;

DTS coding style.

> +		};
> +
> +		cmu_cmu: clock-controller@12400000 {
> +			compatible = "axis,artpec8-cmu-cmu";
> +			reg = <0x12400000 0x4000>;
> +			#clock-cells = <1>;
> +			clocks = <&fin_pll>;
> +			clock-names = "fin_pll";
> +			status = "disabled";

Why? No, don't do that, even if clock frequency of xxti is missing. Look
at other SoCs.


> +		};
> +
> +		cmu_bus: clock-controller@12c10000 {
> +			compatible = "axis,artpec8-cmu-bus";
> +			reg = <0x12c10000 0x4000>;
> +			#clock-cells = <1>;
> +			clocks = <&fin_pll>,
> +				 <&cmu_cmu DOUT_CLKCMU_BUS_BUS>,
> +				 <&cmu_cmu DOUT_CLKCMU_BUS_DLP>;
> +			clock-names = "fin_pll",
> +				      "dout_clkcmu_bus_bus",
> +				      "dout_clkcmu_bus_dlp";
> +			status = "disabled";
> +		};
> +
> +		cmu_core: clock-controller@12410000 {
> +			compatible = "axis,artpec8-cmu-core";
> +			reg = <0x12410000 0x4000>;
> +			#clock-cells = <1>;
> +			clocks = <&fin_pll>,
> +				 <&cmu_cmu DOUT_CLKCMU_CORE_MAIN>,
> +				 <&cmu_cmu DOUT_CLKCMU_CORE_DLP>;
> +			clock-names = "fin_pll",
> +				      "dout_clkcmu_core_main",
> +				      "dout_clkcmu_core_dlp";
> +			status = "disabled";
> +		};
> +
> +		cmu_cpucl: clock-controller@11410000 {
> +			compatible = "axis,artpec8-cmu-cpucl";
> +			reg = <0x11410000 0x4000>;
> +			#clock-cells = <1>;
> +			clocks = <&fin_pll>,
> +				 <&cmu_cmu DOUT_CLKCMU_CPUCL_SWITCH>;
> +			clock-names = "fin_pll",
> +				"dout_clkcmu_cpucl_switch";
> +			status = "disabled";
> +		};
> +
> +		cmu_fsys: clock-controller@16c10000 {
> +			compatible = "axis,artpec8-cmu-fsys";
> +			reg = <0x16c10000 0x4000>;
> +			#clock-cells = <1>;
> +			clocks = <&fin_pll>,
> +				 <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>,
> +				 <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>,
> +				 <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>,
> +				 <&cmu_cmu DOUT_CLKCMU_FSYS_IP>;
> +			clock-names = "fin_pll",
> +				      "dout_clkcmu_fsys_scan0",
> +				      "dout_clkcmu_fsys_scan1",
> +				      "dout_clkcmu_fsys_bus",
> +				      "dout_clkcmu_fsys_ip";
> +			status = "disabled";
> +		};
> +
> +		cmu_imem: clock-controller@10010000 {

DTS coding style.



Best regards,
Krzysztof

Re: [PATCH 14/16] arm64: dts: axis: Add initial device tree support

[sungmin park]

2025-07-10 (목), 09:02 +0200, Krzysztof Kozlowski:
> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> > From: sungminpark <smn1196@coasia.com>
> > 
> > Add initial device tree support for Axis ARTPEC-8 SoC and Grizzly
> > board.
> > This SoC contains four cores of cortex-a53 CPUs and other various
> 
> Subject: Initial device tree of what?

Ok, I will update the patch title in next version.

> 
> > peripheral IPs.
> > 
> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> > Signed-off-by: sungminpark <smn1196@coasia.com>
> > ---
> >  MAINTAINERS                                  |  14 ++
> >  arch/arm64/Kconfig.platforms                 |  13 +
> >  arch/arm64/boot/dts/Makefile                 |   1 +
> >  arch/arm64/boot/dts/axis/Makefile            |   4 +
> >  arch/arm64/boot/dts/axis/artpec8-grizzly.dts |  67 +++++
> >  arch/arm64/boot/dts/axis/artpec8.dtsi        | 252
> > +++++++++++++++++++
> >  6 files changed, 351 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/axis/Makefile
> >  create mode 100644 arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> >  create mode 100644 arch/arm64/boot/dts/axis/artpec8.dtsi
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index fa1e04e87d1d..371005f3f41a 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -2320,6 +2320,20 @@ F:       drivers/crypto/axis
> >  F:     drivers/mmc/host/usdhi6rol0.c
> >  F:     drivers/pinctrl/pinctrl-artpec*
> >  
> > +ARM/ARTPEC ARM64 MACHINE SUPPORT
> 
> This is samsung soc, so I need a pattern for that as well as I will
> be
> handling patches.

Can you please explain what you mean to say?

> 
> > +M:     Jesper Nilsson <jesper.nilsson@axis.com>
> > +M:     Ravi Patel <ravi.patel@samsung.com>
> > +M:     SeonGu Kang <ksk4725@coasia.com>
> > +M:     SungMin Park <smn1196@coasia.com>
> 
> Please keep only maintainers who will actually perform reviews of the
> code. I am not even sure if this is worth separate entry outside of
> Samsung. Please list the IP blocks which are not Samsung here.

Is it fine if I merge the list with existing ARTPEC entry?
Samsung and Coasia entry can be removed from list as Axis will be only
maintaining the ARTPEC-8 SoC in future.
Please suggest your opinion here.

> 
> > +L:     linux-arm-kernel@lists.infradead.org (moderated for non-
> > subscribers)
> > +L:     linux-samsung-soc@vger.kernel.org
> > +L:     linux-arm-kernel@axis.com
> > +S:     Maintained
> > +F:     Documentation/devicetree/bindings/clock/axis,artpec*-
> > clock.yaml
> > +F:     arch/arm64/boot/dts/axis/
> > +F:     drivers/clk/samsung/clk-artpec*.c
> > +F:     include/dt-bindings/clock/axis,artpec*-clk.h
> > +
> >  ARM/ASPEED I2C DRIVER
> >  M:     Ryan Chen <ryan_chen@aspeedtech.com>
> >  R:     Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > diff --git a/arch/arm64/Kconfig.platforms
> > b/arch/arm64/Kconfig.platforms
> > index 8b76821f190f..418ee47227c1 100644
> > --- a/arch/arm64/Kconfig.platforms
> > +++ b/arch/arm64/Kconfig.platforms
> > @@ -40,6 +40,19 @@ config ARCH_APPLE
> >           This enables support for Apple's in-house ARM SoC family,
> > such
> >           as the Apple M1.
> >  
> > +config ARCH_ARTPEC
> > +       bool "Axis Communications ARTPEC SoC Family"
> > +       help
> > +          This enables support for the ARMv8 based ARTPEC SoC
> > Family.
> > +
> > +config ARCH_ARTPEC8
> 
> No, drop. One ARCH symbol.
> 
> > +       bool "Axis ARTPEC-8 SoC Platform"
> > +       depends on ARCH_ARTPEC
> > +       depends on ARCH_EXYNOS
> 
> And that's the proof that this is Samsung SoC.

Should I move the axis folder inside exynos just like google did? In
that case we don't need separate ARCH entry anymore.
Or should I follow the tesla FSD style to add axis folder outside
exynos? In that case I will keep ARCH_ARTPEC entry only.
Please suggest your opinion here.

> 
> > +       select ARM_GIC
> > +       help
> > +         This enables support for the Axis ARTPEC-8 SoC.
> > +
> >  menuconfig ARCH_BCM
> >         bool "Broadcom SoC Support"
> >  
> > diff --git a/arch/arm64/boot/dts/Makefile
> > b/arch/arm64/boot/dts/Makefile
> > index 79b73a21ddc2..6b6a3aedc2ed 100644
> > --- a/arch/arm64/boot/dts/Makefile
> > +++ b/arch/arm64/boot/dts/Makefile
> > @@ -9,6 +9,7 @@ subdir-y += amlogic
> >  subdir-y += apm
> >  subdir-y += apple
> >  subdir-y += arm
> > +subdir-y += axis
> >  subdir-y += bitmain
> >  subdir-y += blaize
> >  subdir-y += broadcom
> > diff --git a/arch/arm64/boot/dts/axis/Makefile
> > b/arch/arm64/boot/dts/axis/Makefile
> > new file mode 100644
> > index 000000000000..ccf00de64016
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/axis/Makefile
> > @@ -0,0 +1,4 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +dtb-$(CONFIG_ARCH_ARTPEC) += \
> > +       artpec8-grizzly.dtb
> > diff --git a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> > b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> > new file mode 100644
> > index 000000000000..7671130a0333
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> > @@ -0,0 +1,67 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Axis ARTPEC-8 Grizzly board device tree source
> > + *
> > + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> > + *             https://www.samsung.com
> > + * Copyright (c) 2022-2025  Axis Communications AB.
> > + *             https://www.axis.com
> > + */
> > +
> > +/dts-v1/;
> > +#include "artpec8.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +/ {
> > +       model = "ARTPEC-8 grizzly board";
> > +       compatible = "axis,artpec8-grizzly", "axis,artpec8";
> > +
> > +       aliases {
> > +               serial0 = &serial_0;
> > +       };
> > +
> > +       chosen {
> > +               stdout-path = &serial_0;
> > +       };
> > +
> > +       memory@80000000 {
> > +               device_type = "memory";
> > +               reg = <0x0 0x80000000 0x0 0x80000000>;
> > +       };
> > +};
> > +
> > +&osc_clk {
> > +       clock-frequency = <50000000>;
> > +       status = "okay";
> 
> Why?

Ok, I will remove status property.

> 
> > +};
> > +
> > +&serial_0 {
> 
> Follow DTS coding style. s > c
> o > c

Ok, I will reorder the nodes in alphabetical order.

> 
> 
> > +       status = "okay";
> > +};
> > +
> > +&cmu_cmu {
> > +       status = "okay";
> > +};
> > +
> > +&cmu_bus {
> > +       status = "okay";
> > +};
> > +
> > +&cmu_core {
> > +       status = "okay";
> > +};
> > +
> > +&cmu_cpucl {
> > +       status = "okay";
> > +};
> > +
> > +&cmu_fsys {
> > +       status = "okay";
> > +};
> > +
> > +&cmu_imem {
> > +       status = "okay";
> > +};
> > +
> > +&cmu_peri {
> > +       status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/axis/artpec8.dtsi
> > b/arch/arm64/boot/dts/axis/artpec8.dtsi
> > new file mode 100644
> > index 000000000000..296192560adf
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/axis/artpec8.dtsi
> > @@ -0,0 +1,252 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Axis ARTPEC-8 SoC device tree source
> > + *
> > + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> > + *             https://www.samsung.com
> > + * Copyright (c) 2022-2025  Axis Communications AB.
> > + *             https://www.axis.com
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/clock/axis,artpec8-clk.h>
> > +
> > +/ {
> > +       compatible = "axis,artpec8";
> > +       interrupt-parent = <&gic>;
> > +       #address-cells = <2>;
> > +       #size-cells = <2>;
> > +
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x0>;
> > +                       cpu-idle-states = <&cpu_sleep>;
> > +                       enable-method = "psci";
> > +                       clocks = <&cmu_cpucl DOUT_CLK_CPUCL_CPU>;
> > +                       clock-names = "dout_clk_cpucl_cpu";
> > +                       clock-frequency = <1200000000>;
> 
> This feels wrong. Frequency changes, doesn't it?

Ok, I will remove the “clock-frequency” property in the next version.

> 
> > +               };
> > +
> > +               cpu1: cpu@1 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x1>;
> > +                       cpu-idle-states = <&cpu_sleep>;
> > +                       enable-method = "psci";
> > +                       clock-frequency = <1200000000>;
> > +               };
> > +
> > +               cpu2: cpu@2 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x2>;
> > +                       cpu-idle-states = <&cpu_sleep>;
> > +                       enable-method = "psci";
> > +                       clock-frequency = <1200000000>;
> > +               };
> > +
> > +               cpu3: cpu@3 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x3>;
> > +                       cpu-idle-states = <&cpu_sleep>;
> > +                       enable-method = "psci";
> > +                       clock-frequency = <1200000000>;
> > +               };
> > +
> > +               idle-states {
> > +                       entry-method = "psci";
> > +
> > +                       cpu_sleep: cpu-sleep {
> > +                               compatible = "arm,idle-state";
> > +                               arm,psci-suspend-param =
> > <0x0010000>;
> > +                               local-timer-stop;
> > +                               entry-latency-us = <300>;
> > +                               exit-latency-us = <1200>;
> > +                               min-residency-us = <2000>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       timer {
> 
> Also wrongly ordered. See DTS coding style.

Ok, I will reorder the nodes in alphabetical order.

> 
> 
> > +               compatible = "arm,armv8-timer";
> > +               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > +                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > +                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > +                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > +       };
> > +
> > +       pmu {
> > +               compatible = "arm,cortex-a53-pmu";
> > +               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> > +               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
> > <&cpu3>;
> > +       };
> > +
> > +       psci {
> > +               compatible = "arm,psci-0.2";
> > +               method = "smc";
> > +       };
> > +
> > +       osc_clk: xxti {
> 
> clock-xxti

Ok, I will rename node name to clock-xxti.

> 
> > +               compatible = "fixed-clock";
> > +               clock-output-names = "xxti";
> > +               #clock-cells = <0>;
> > +       };
> > +
> > +       fin_pll: fin_pll {
> 
> DTS coding style.

Ok, I will rename the label to clock_finpll.

> 
> > +               compatible = "fixed-factor-clock";
> > +               clocks = <&osc_clk>;
> > +               #clock-cells = <0>;
> > +               clock-div = <2>;
> > +               clock-mult = <1>;
> > +               clock-output-names = "fin_pll";
> > +       };
> > +
> > +       soc: soc@0 {
> > +               compatible = "simple-bus";
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +               ranges = <0x0 0x0 0x0 0x17000000>;
> 
> DTS coding style.

Ok, I will move the ranges property next to compatible.

> 
> > +
> > +               mct@10040000 {
> 
> Look at other SoCs first
> 
> > +                       compatible = "samsung,exynos4210-mct";
> 
> You just missed two years of development, right? Look at other SoCs.

Ok, I will add “axis,artpec8-mct” in the compatible string and rename
the node name to "timer".

> 
> 
> > +                       reg = <0x10040000 0x1000>;
> > +                       clocks = <&fin_pll>, <&cmu_imem
> > MOUT_IMEM_ACLK_USER>;
> > +                       clock-names = "fin_pll", "mct";
> > +                       interrupts = <GIC_SPI 455
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 456
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 457
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 458
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 459
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 460
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 461
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 462
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 463
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 464
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 465
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 466
> > IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               gic: interrupt-controller@10201000 {
> > +                       compatible = "arm,gic-400";
> > +                       #interrupt-cells = <3>;
> > +                       #address-cells = <0>;
> > +                       interrupt-controller;
> > +                       reg = <0x10201000 0x00001000>,
> > +                             <0x10202000 0x00002000>,
> > +                             <0x10204000 0x00002000>,
> > +                             <0x10206000 0x00002000>;
> 
> DTS coding style.

Ok, I will move the reg property next to compatible.

> 
> > +               };
> > +
> > +               cmu_cmu: clock-controller@12400000 {
> > +                       compatible = "axis,artpec8-cmu-cmu";
> > +                       reg = <0x12400000 0x4000>;
> > +                       #clock-cells = <1>;
> > +                       clocks = <&fin_pll>;
> > +                       clock-names = "fin_pll";
> > +                       status = "disabled";
> 
> Why? No, don't do that, even if clock frequency of xxti is missing.
> Look
> at other SoCs.

Ok, I will remove status property from clock-controller nodes.
The clock frequency of xxti is added in board dts file.

> 
> 
> > +               };
> > +
> > +               cmu_bus: clock-controller@12c10000 {
> > +                       compatible = "axis,artpec8-cmu-bus";
> > +                       reg = <0x12c10000 0x4000>;
> > +                       #clock-cells = <1>;
> > +                       clocks = <&fin_pll>,
> > +                                <&cmu_cmu DOUT_CLKCMU_BUS_BUS>,
> > +                                <&cmu_cmu DOUT_CLKCMU_BUS_DLP>;
> > +                       clock-names = "fin_pll",
> > +                                     "dout_clkcmu_bus_bus",
> > +                                     "dout_clkcmu_bus_dlp";
> > +                       status = "disabled";
> > +               };
> > +
> > +               cmu_core: clock-controller@12410000 {
> > +                       compatible = "axis,artpec8-cmu-core";
> > +                       reg = <0x12410000 0x4000>;
> > +                       #clock-cells = <1>;
> > +                       clocks = <&fin_pll>,
> > +                                <&cmu_cmu DOUT_CLKCMU_CORE_MAIN>,
> > +                                <&cmu_cmu DOUT_CLKCMU_CORE_DLP>;
> > +                       clock-names = "fin_pll",
> > +                                     "dout_clkcmu_core_main",
> > +                                     "dout_clkcmu_core_dlp";
> > +                       status = "disabled";
> > +               };
> > +
> > +               cmu_cpucl: clock-controller@11410000 {
> > +                       compatible = "axis,artpec8-cmu-cpucl";
> > +                       reg = <0x11410000 0x4000>;
> > +                       #clock-cells = <1>;
> > +                       clocks = <&fin_pll>,
> > +                                <&cmu_cmu
> > DOUT_CLKCMU_CPUCL_SWITCH>;
> > +                       clock-names = "fin_pll",
> > +                               "dout_clkcmu_cpucl_switch";
> > +                       status = "disabled";
> > +               };
> > +
> > +               cmu_fsys: clock-controller@16c10000 {
> > +                       compatible = "axis,artpec8-cmu-fsys";
> > +                       reg = <0x16c10000 0x4000>;
> > +                       #clock-cells = <1>;
> > +                       clocks = <&fin_pll>,
> > +                                <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>,
> > +                                <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>,
> > +                                <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>,
> > +                                <&cmu_cmu DOUT_CLKCMU_FSYS_IP>;
> > +                       clock-names = "fin_pll",
> > +                                     "dout_clkcmu_fsys_scan0",
> > +                                     "dout_clkcmu_fsys_scan1",
> > +                                     "dout_clkcmu_fsys_bus",
> > +                                     "dout_clkcmu_fsys_ip";
> > +                       status = "disabled";
> > +               };
> > +
> > +               cmu_imem: clock-controller@10010000 {
> 
> DTS coding style.

Ok, I will sort the cmu nodes according to their address.

Thanks,
sungminpark

> 
> 
> 
> Best regards,
> Krzysztof

Re: [PATCH 14/16] arm64: dts: axis: Add initial device tree support

[Krzysztof Kozlowski]

On 21/07/2025 09:08, sungmin park wrote:
>>> index fa1e04e87d1d..371005f3f41a 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -2320,6 +2320,20 @@ F:       drivers/crypto/axis
>>>  F:     drivers/mmc/host/usdhi6rol0.c
>>>  F:     drivers/pinctrl/pinctrl-artpec*
>>>  
>>> +ARM/ARTPEC ARM64 MACHINE SUPPORT
>>
>> This is samsung soc, so I need a pattern for that as well as I will
>> be
>> handling patches.
> 
> Can you please explain what you mean to say?


Something like I sent for Tesla the same day or shortly after I
commented on this.

>  
>>
>>> +M:     Jesper Nilsson <jesper.nilsson@axis.com>
>>> +M:     Ravi Patel <ravi.patel@samsung.com>
>>> +M:     SeonGu Kang <ksk4725@coasia.com>
>>> +M:     SungMin Park <smn1196@coasia.com>
>>
>> Please keep only maintainers who will actually perform reviews of the
>> code. I am not even sure if this is worth separate entry outside of
>> Samsung. Please list the IP blocks which are not Samsung here.

Are you going to implement this in the next patch?

> 
> Is it fine if I merge the list with existing ARTPEC entry?

No. Did you read my message? I am not maintainer of existing ARTPEC SoC.


> Samsung and Coasia entry can be removed from list as Axis will be only
> maintaining the ARTPEC-8 SoC in future.
> Please suggest your opinion here.
> 
>>
>>> +L:     linux-arm-kernel@lists.infradead.org (moderated for non-
>>> subscribers)
>>> +L:     linux-samsung-soc@vger.kernel.org
>>> +L:     linux-arm-kernel@axis.com
>>> +S:     Maintained
>>> +F:     Documentation/devicetree/bindings/clock/axis,artpec*-
>>> clock.yaml
>>> +F:     arch/arm64/boot/dts/axis/
>>> +F:     drivers/clk/samsung/clk-artpec*.c
>>> +F:     include/dt-bindings/clock/axis,artpec*-clk.h
>>> +
>>>  ARM/ASPEED I2C DRIVER
>>>  M:     Ryan Chen <ryan_chen@aspeedtech.com>
>>>  R:     Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>> diff --git a/arch/arm64/Kconfig.platforms
>>> b/arch/arm64/Kconfig.platforms
>>> index 8b76821f190f..418ee47227c1 100644
>>> --- a/arch/arm64/Kconfig.platforms
>>> +++ b/arch/arm64/Kconfig.platforms
>>> @@ -40,6 +40,19 @@ config ARCH_APPLE
>>>           This enables support for Apple's in-house ARM SoC family,
>>> such
>>>           as the Apple M1.
>>>  
>>> +config ARCH_ARTPEC
>>> +       bool "Axis Communications ARTPEC SoC Family"
>>> +       help
>>> +          This enables support for the ARMv8 based ARTPEC SoC
>>> Family.
>>> +
>>> +config ARCH_ARTPEC8
>>
>> No, drop. One ARCH symbol.
>>
>>> +       bool "Axis ARTPEC-8 SoC Platform"
>>> +       depends on ARCH_ARTPEC
>>> +       depends on ARCH_EXYNOS
>>
>> And that's the proof that this is Samsung SoC.
> 
> Should I move the axis folder inside exynos just like google did? In
> that case we don't need separate ARCH entry anymore.
> Or should I follow the tesla FSD style to add axis folder outside
> exynos? In that case I will keep ARCH_ARTPEC entry only.
> Please suggest your opinion here.


You did not describe the hardware really. Neither in commit msg, nor in
cover letter nor here where I asked to list the non-Samsung IP blocks. I
will not provide you guidelines based on magic crystal ball guesses.


Best regards,
Krzysztof

Re: [PATCH 14/16] arm64: dts: axis: Add initial device tree support

[Arnd Bergmann]

On Thu, Jul 10, 2025, at 02:20, ksk4725@coasia.com wrote:
> From: sungminpark <smn1196@coasia.com>
>
> Add initial device tree support for Axis ARTPEC-8 SoC and Grizzly board.
> This SoC contains four cores of cortex-a53 CPUs and other various
> peripheral IPs.

> diff --git a/MAINTAINERS b/MAINTAINERS
> index fa1e04e87d1d..371005f3f41a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2320,6 +2320,20 @@ F:	drivers/crypto/axis
>  F:	drivers/mmc/host/usdhi6rol0.c
>  F:	drivers/pinctrl/pinctrl-artpec*
> 
> +ARM/ARTPEC ARM64 MACHINE SUPPORT
> +M:	Jesper Nilsson <jesper.nilsson@axis.com>
> +M:	Ravi Patel <ravi.patel@samsung.com>
> +M:	SeonGu Kang <ksk4725@coasia.com>
> +M:	SungMin Park <smn1196@coasia.com>
> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +L:	linux-samsung-soc@vger.kernel.org
> +L:	linux-arm-kernel@axis.com
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml
> +F:	arch/arm64/boot/dts/axis/
> +F:	drivers/clk/samsung/clk-artpec*.c
> +F:	include/dt-bindings/clock/axis,artpec*-clk.h

I'm trying to understand the SoC family tree here. I see that
you have an entry for ARTPEC SoCs above it, which currently
covers artpec6 (Cortex-A9, apparently not Samsung based).

Is the reason for having two entries here that artpec6/7 and
artpec8/9 are two separate SoC families, or is this just because
they are using 32-bit and 64-bit cores, respectively?

> 
> +config ARCH_ARTPEC
> +	bool "Axis Communications ARTPEC SoC Family"
> +	help
> +	   This enables support for the ARMv8 based ARTPEC SoC Family.
> +
> +config ARCH_ARTPEC8
> +	bool "Axis ARTPEC-8 SoC Platform"
> +	depends on ARCH_ARTPEC
> +	depends on ARCH_EXYNOS
> +	select ARM_GIC
> +	help
> +	  This enables support for the Axis ARTPEC-8 SoC.
> +

I would prefer to be less fine-grained here, especially as
it seems that ARTPEC9 is again quite similar to ARTPEC8, as
far as I can guess from public information.

Could you fold both entries into a single ARCH_ARTPEC?

     Arnd

Re: [PATCH 14/16] arm64: dts: axis: Add initial device tree support

[Krzysztof Kozlowski]

On 10/07/2025 09:48, Arnd Bergmann wrote:
> On Thu, Jul 10, 2025, at 02:20, ksk4725@coasia.com wrote:
>> From: sungminpark <smn1196@coasia.com>
>>
>> Add initial device tree support for Axis ARTPEC-8 SoC and Grizzly board.
>> This SoC contains four cores of cortex-a53 CPUs and other various
>> peripheral IPs.
> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index fa1e04e87d1d..371005f3f41a 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2320,6 +2320,20 @@ F:	drivers/crypto/axis
>>  F:	drivers/mmc/host/usdhi6rol0.c
>>  F:	drivers/pinctrl/pinctrl-artpec*
>>
>> +ARM/ARTPEC ARM64 MACHINE SUPPORT
>> +M:	Jesper Nilsson <jesper.nilsson@axis.com>
>> +M:	Ravi Patel <ravi.patel@samsung.com>
>> +M:	SeonGu Kang <ksk4725@coasia.com>
>> +M:	SungMin Park <smn1196@coasia.com>
>> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>> +L:	linux-samsung-soc@vger.kernel.org
>> +L:	linux-arm-kernel@axis.com
>> +S:	Maintained
>> +F:	Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml
>> +F:	arch/arm64/boot/dts/axis/
>> +F:	drivers/clk/samsung/clk-artpec*.c
>> +F:	include/dt-bindings/clock/axis,artpec*-clk.h
> 
> I'm trying to understand the SoC family tree here. I see that
> you have an entry for ARTPEC SoCs above it, which currently
> covers artpec6 (Cortex-A9, apparently not Samsung based).
> 
> Is the reason for having two entries here that artpec6/7 and
> artpec8/9 are two separate SoC families, or is this just because
> they are using 32-bit and 64-bit cores, respectively?

These should be entirely different families. Artpec6 was not done by
Samsung and this one - Artpec 8 - is basically Samsung SoC, just like
they did designs for Tesla and Google GS101.

I don't know about Artpec 9.

All this should be explained in DTS or bindings commit msg, btw.

> 
>>
>> +config ARCH_ARTPEC
>> +	bool "Axis Communications ARTPEC SoC Family"
>> +	help
>> +	   This enables support for the ARMv8 based ARTPEC SoC Family.
>> +
>> +config ARCH_ARTPEC8
>> +	bool "Axis ARTPEC-8 SoC Platform"
>> +	depends on ARCH_ARTPEC
>> +	depends on ARCH_EXYNOS
>> +	select ARM_GIC
>> +	help
>> +	  This enables support for the Axis ARTPEC-8 SoC.
>> +
> 
> I would prefer to be less fine-grained here, especially as
> it seems that ARTPEC9 is again quite similar to ARTPEC8, as
> far as I can guess from public information.
> 
> Could you fold both entries into a single ARCH_ARTPEC?

So far ARCH_ARTPEC = ARCH_ARTPEC8, so obviously it can be folded. I
don't know if Artpec 9 will ever be upstreamed. This Artpec 8 is like 4
or 5 year effort - they sent first patches some years ago, but DTS was
not ready. Therefore I think we should not assume there will be Artpec 9
yet. If it comes, we can always split things.


Best regards,
Krzysztof

[PATCH 15/16] arm64: dts: axis: Add initial pinctrl support

[ksk4725]

From: SeonGu Kang <ksk4725@coasia.com>

Add initial pin configuration nodes for the Axis ARTPEC-8 SoC.

Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
---
 arch/arm64/boot/dts/axis/artpec-pinctrl.h     |  36 ++
 arch/arm64/boot/dts/axis/artpec8-grizzly.dts  |   1 +
 arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi | 373 ++++++++++++++++++
 arch/arm64/boot/dts/axis/artpec8.dtsi         |  17 +
 4 files changed, 427 insertions(+)
 create mode 100644 arch/arm64/boot/dts/axis/artpec-pinctrl.h
 create mode 100644 arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi

diff --git a/arch/arm64/boot/dts/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/axis/artpec-pinctrl.h
new file mode 100644
index 000000000000..c2c1e25b7f6a
--- /dev/null
+++ b/arch/arm64/boot/dts/axis/artpec-pinctrl.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Axis ARTPEC-8 SoC device tree pinctrl constants
+ *
+ * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2022-2025  Axis Communications AB.
+ *             https://www.axis.com
+ */
+
+#ifndef __DTS_ARM64_AXIS_ARTPEC_PINCTRL_H__
+#define __DTS_ARM64_AXIS_ARTPEC_PINCTRL_H__
+
+#define ARTPEC_PIN_PULL_NONE		0
+#define ARTPEC_PIN_PULL_DOWN		1
+#define ARTPEC_PIN_PULL_UP		3
+
+#define ARTPEC_PIN_FUNC_INPUT		0
+#define ARTPEC_PIN_FUNC_OUTPUT		1
+#define ARTPEC_PIN_FUNC_2		2
+#define ARTPEC_PIN_FUNC_3		3
+#define ARTPEC_PIN_FUNC_4		4
+#define ARTPEC_PIN_FUNC_5		5
+#define ARTPEC_PIN_FUNC_6		6
+#define ARTPEC_PIN_FUNC_EINT		0xf
+#define ARTPEC_PIN_FUNC_F		ARTPEC_PIN_FUNC_EINT
+
+/* Drive strength for ARTPEC */
+#define ARTPEC_PIN_DRV_SR1		0x8
+#define ARTPEC_PIN_DRV_SR2		0x9
+#define ARTPEC_PIN_DRV_SR3		0xa
+#define ARTPEC_PIN_DRV_SR4		0xb
+#define ARTPEC_PIN_DRV_SR5		0xc
+#define ARTPEC_PIN_DRV_SR6		0xd
+
+#endif /* __DTS_ARM64_AXIS_ARTPEC_PINCTRL_H__ */
diff --git a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
index 7671130a0333..f14420e76188 100644
--- a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
+++ b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
@@ -10,6 +10,7 @@
 
 /dts-v1/;
 #include "artpec8.dtsi"
+#include "artpec8-pinctrl.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 / {
 	model = "ARTPEC-8 grizzly board";
diff --git a/arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi
new file mode 100644
index 000000000000..2d22a8be9d61
--- /dev/null
+++ b/arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2022-2025  Axis Communications AB.
+ *             https://www.axis.com
+ */
+
+#include "artpec-pinctrl.h"
+
+&pinctrl_fsys {
+	serial0_bus: serial0-bus-pins {
+		samsung,pins = "gpf4-4", "gpf4-5";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	qspi_clk: qspi-clk-pins {
+		samsung,pins = "gpf0-2";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_4>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	qspi_data: qspi-data-pins {
+		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_4>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	gpf0: gpf0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf1: gpf1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf2: gpf2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf3: gpf3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf4: gpf4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpe0: gpe0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpe1: gpe1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpe2: gpe2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gps0: gps0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gps1: gps1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	hsi2c0_bus: hsi2c0-bus-pins {
+		samsung,pins = "gpf4-0", "gpf4-1";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	hsi2c1_bus: hsi2c1-bus-pins {
+		samsung,pins = "gpf4-2", "gpf4-3";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	pwm0_out: pwm0-out-pins {
+		samsung,pins = "gpf3-0";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	pwm1_out: pwm1-out-pins {
+		samsung,pins = "gpf3-1";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	pwm2_out: pwm2-out-pins {
+		samsung,pins = "gpf3-2";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	pwm3_out: pwm3-out-pins {
+		samsung,pins = "gpf3-3";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc0_clk: mmc0-clk-pins {
+		samsung,pins = "gps0-0";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc0_bus: mmc0-bus-pins {
+		samsung,pins = "gps0-1", "gps0-2", "gps0-3", "gps0-4", "gps0-5";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc0_cd: mmc0-cd-pins {
+		samsung,pins = "gps0-6";
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc0_wp: mmc0-wp-pins {
+		samsung,pins = "gps0-7";
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc0_rst: mmc0-rst-pins {
+		samsung,pins = "gps0-7";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc1_clk: mmc1-clk-pins {
+		samsung,pins = "gps1-0";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc1_bus: mmc1-bus-pins {
+		samsung,pins = "gps1-1", "gps1-2", "gps1-3", "gps1-4", "gps1-5";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc1_cd: mmc1-cd-pins {
+		samsung,pins = "gps1-6";
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc1_wp: mmc1-wp-pins {
+		samsung,pins = "gps1-7";
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	mmc1_rst: mmc1-rst-pins {
+		samsung,pins = "gps1-7";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_DOWN>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	eth_gpio: eth-gpio-pins {
+		samsung,pins = "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-3", "gpe1-4",
+			       "gpe1-5", "gpe1-6", "gpe1-7", "gpe0-0", "gpe0-1",
+			       "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6",
+			       "gpe0-7", "gpe2-1";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	eth_mdio: eth-mdio-pins {
+		samsung,pins = "gpe2-0";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	eth_ref_clk: eth-ref-clk-pins {
+		samsung,pins = "gpe2-2";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	eth_gtx_clk: eth-gtx-clk-pins {
+		samsung,pins = "gpe2-2";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	eth_phy_intr: eth-phy-intr-pins {
+		samsung,pins = "gpe2-4";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_DOWN>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	eth_pps: eth-pps-pins {
+		samsung,pins = "gpf4-6";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	sfmc_ctrl: sfmc-ctrl-pins {
+		samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+			       "gpf0-4", "gpf1-0", "gpf1-1", "gpf1-2";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	sfmc_io: sfmc-io-pins {
+		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4",
+			       "gpf2-5", "gpf2-6", "gpf2-7";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_NONE>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+};
+
+&pinctrl_peric {
+	serial1_bus: serial1-bus-pins {
+		samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	serial2_bus: serial2-bus-pins {
+		samsung,pins = "gpa2-4", "gpa2-5", "gpa2-6", "gpa2-7";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	spi0_bus: spi0-bus-pins {
+		samsung,pins = "gpa0-0", "gpa0-1", "gpa0-2", "gpa0-3";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	spi0_bus_nocs: spi0-bus-nocs-pins {
+		samsung,pins = "gpa0-0", "gpa0-1", "gpa0-2";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	gpa0: gpa0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpa1: gpa1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpa2: gpa2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpk0: gpk0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	i2s0_bus: i2s0-bus-pins {
+		samsung,pins = "gpa1-4", "gpa1-5", "gpa1-6", "gpa1-7";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	i2s0_idle: i2s0-idle-pins {
+		samsung,pins = "gpa1-4", "gpa1-5", "gpa1-6", "gpa1-7";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	i2s1_bus: i2s1-bus-pins {
+		samsung,pins = "gpa1-0", "gpa1-1", "gpa1-2", "gpa1-3";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	i2s1_idle: i2s1-idle-pins {
+		samsung,pins = "gpa1-0", "gpa1-1", "gpa1-2", "gpa1-3";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_INPUT>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	hsi2c2_bus: hsi2c2-bus-pins {
+		samsung,pins = "gpa0-6", "gpa0-7";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+
+	hsi2c3_bus: hsi2c3-bus-pins {
+		samsung,pins = "gpa0-4", "gpa0-5";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+};
diff --git a/arch/arm64/boot/dts/axis/artpec8.dtsi b/arch/arm64/boot/dts/axis/artpec8.dtsi
index 296192560adf..9c2afbac75b9 100644
--- a/arch/arm64/boot/dts/axis/artpec8.dtsi
+++ b/arch/arm64/boot/dts/axis/artpec8.dtsi
@@ -17,6 +17,11 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		pinctrl0 = &pinctrl_fsys;
+		pinctrl1 = &pinctrl_peric;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -237,6 +242,18 @@ cmu_peri: clock-controller@16410000 {
 			status = "disabled";
 		};
 
+		pinctrl_fsys: pinctrl@16c30000 {
+			compatible = "axis,artpec8-pinctrl";
+			reg = <0x16c30000 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_peric: pinctrl@165f0000 {
+			compatible = "axis,artpec8-pinctrl";
+			reg = <0x165f0000 0x1000>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		serial_0: serial@16cc0000 {
 			compatible = "axis,artpec8-uart";
 			reg = <0x16cc0000 0x100>;
-- 
2.34.1

Re: [PATCH 15/16] arm64: dts: axis: Add initial pinctrl support

[Krzysztof Kozlowski]

On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> From: SeonGu Kang <ksk4725@coasia.com>
> 
> Add initial pin configuration nodes for the Axis ARTPEC-8 SoC.
> 
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> ---
>  arch/arm64/boot/dts/axis/artpec-pinctrl.h     |  36 ++
>  arch/arm64/boot/dts/axis/artpec8-grizzly.dts  |   1 +
>  arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi | 373 ++++++++++++++++++
>  arch/arm64/boot/dts/axis/artpec8.dtsi         |  17 +

This belongs to the previous patch rather. You can split board DTS, though.

>  4 files changed, 427 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/axis/artpec-pinctrl.h
>  create mode 100644 arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi
> 
> diff --git a/arch/arm64/boot/dts/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/axis/artpec-pinctrl.h
> new file mode 100644
> index 000000000000..c2c1e25b7f6a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axis/artpec-pinctrl.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Axis ARTPEC-8 SoC device tree pinctrl constants
> + *
> + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.

First publish date was 2025, not 2022, so all these copyrights feel wrong.

> + *             https://www.samsung.com
> + * Copyright (c) 2022-2025  Axis Communications AB.
> + *             https://www.axis.com
> + */
> +


...

> +	i2s0_idle: i2s0-idle-pins {
> +		samsung,pins = "gpa1-4", "gpa1-5", "gpa1-6", "gpa1-7";
> +		samsung,pin-function = <ARTPEC_PIN_FUNC_INPUT>;
> +		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
> +		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
> +	};
> +
> +	i2s1_bus: i2s1-bus-pins {
> +		samsung,pins = "gpa1-0", "gpa1-1", "gpa1-2", "gpa1-3";
> +		samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
> +		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
> +		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
> +	};
> +
> +	i2s1_idle: i2s1-idle-pins {
> +		samsung,pins = "gpa1-0", "gpa1-1", "gpa1-2", "gpa1-3";
> +		samsung,pin-function = <ARTPEC_PIN_FUNC_INPUT>;
> +		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
> +		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
> +	};
> +
> +	hsi2c2_bus: hsi2c2-bus-pins {
> +		samsung,pins = "gpa0-6", "gpa0-7";

We sort nodes by pin names, usually. What sorting rule you applied here?



Best regards,
Krzysztof

Re: [PATCH 15/16] arm64: dts: axis: Add initial pinctrl support

[SeonGu Kang]

2025-07-10 (목), 09:04 +0200, Krzysztof Kozlowski:
> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> > From: SeonGu Kang <ksk4725@coasia.com>
> > 
> > Add initial pin configuration nodes for the Axis ARTPEC-8 SoC.
> > 
> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> > Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> > ---
> >  arch/arm64/boot/dts/axis/artpec-pinctrl.h     |  36 ++
> >  arch/arm64/boot/dts/axis/artpec8-grizzly.dts  |   1 +
> >  arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi | 373
> > ++++++++++++++++++
> >  arch/arm64/boot/dts/axis/artpec8.dtsi         |  17 +
> 
> This belongs to the previous patch rather. You can split board DTS,
> though.

Ok, I will move the dtsi changes to previous patch

> 
> >  4 files changed, 427 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/axis/artpec-pinctrl.h
> >  create mode 100644 arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/axis/artpec-pinctrl.h
> > b/arch/arm64/boot/dts/axis/artpec-pinctrl.h
> > new file mode 100644
> > index 000000000000..c2c1e25b7f6a
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/axis/artpec-pinctrl.h
> > @@ -0,0 +1,36 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Axis ARTPEC-8 SoC device tree pinctrl constants
> > + *
> > + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> 
> First publish date was 2025, not 2022, so all these copyrights feel
> wrong.
> 

Ok, I will update the copyright year to 2025 only

> > + *             https://www.samsung.com
> > + * Copyright (c) 2022-2025  Axis Communications AB.
> > + *             https://www.axis.com
> > + */
> > +
> 
> 
> ...
> 
> > +       i2s0_idle: i2s0-idle-pins {
> > +               samsung,pins = "gpa1-4", "gpa1-5", "gpa1-6", "gpa1-
> > 7";
> > +               samsung,pin-function = <ARTPEC_PIN_FUNC_INPUT>;
> > +               samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
> > +               samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
> > +       };
> > +
> > +       i2s1_bus: i2s1-bus-pins {
> > +               samsung,pins = "gpa1-0", "gpa1-1", "gpa1-2", "gpa1-
> > 3";
> > +               samsung,pin-function = <ARTPEC_PIN_FUNC_3>;
> > +               samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
> > +               samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
> > +       };
> > +
> > +       i2s1_idle: i2s1-idle-pins {
> > +               samsung,pins = "gpa1-0", "gpa1-1", "gpa1-2", "gpa1-
> > 3";
> > +               samsung,pin-function = <ARTPEC_PIN_FUNC_INPUT>;
> > +               samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
> > +               samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
> > +       };
> > +
> > +       hsi2c2_bus: hsi2c2-bus-pins {
> > +               samsung,pins = "gpa0-6", "gpa0-7";
> 
> We sort nodes by pin names, usually. What sorting rule you applied
> here?
> 

Ok, I will sort the pin nodes alphabatically

> 
> 
> Best regards,
> Krzysztof

[PATCH 16/16] arm64: defconfig: Enable Axis ARTPEC SoC

[ksk4725]

From: sungminpark <smn1196@coasia.com>

Enable the Axis ARTPEC-8 SoC in arm64 defconfig.

Signed-off-by: sungminpark <smn1196@coasia.com>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5bb8f09422a2..00b902c2d997 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -38,6 +38,8 @@ CONFIG_ARCH_AIROHA=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_APPLE=y
+CONFIG_ARCH_ARTPEC=y
+CONFIG_ARCH_ARTPEC8=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM2835=y
 CONFIG_ARCH_BCM_IPROC=y
-- 
2.34.1

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Krzysztof Kozlowski]

On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> From: SeonGu Kang <ksk4725@coasia.com>
> 
> Add basic support for the Axis ARTPEC-8 SoC.
> This SoC contains four Cortex-A53 CPUs and other several IPs.
> 
> Patches 1 to 10 provide the support for the clock controller,
> which is similar to other Samsung SoCs.
> 
You should explain here (and in DTS patches or the bindings) the
hardware, that this is Samsung SoC.

You could also explain the differences from Exynos and proposed handling
of patches (because this is odd)

Also, entire patchset has wrong and incomplete SoBs. Your SoB is missing
everywhere, others have wrong order.

Please read submitting patches first.


Best regards,
Krzysztof

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[SeonGu Kang]

2025-07-10 (목), 09:07 +0200, Krzysztof Kozlowski:
> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> > From: SeonGu Kang <ksk4725@coasia.com>
> > 
> > Add basic support for the Axis ARTPEC-8 SoC.
> > This SoC contains four Cortex-A53 CPUs and other several IPs.
> > 
> > Patches 1 to 10 provide the support for the clock controller,
> > which is similar to other Samsung SoCs.
> > 
> You should explain here (and in DTS patches or the bindings) the
> hardware, that this is Samsung SoC.
> 
> You could also explain the differences from Exynos and proposed
> handling
> of patches (because this is odd)
> 
> Also, entire patchset has wrong and incomplete SoBs. Your SoB is
> missing
> everywhere, others have wrong order.
> 
> Please read submitting patches first.
> 

This Custom SoC is owned by the Axis (OEM) and manufactured by the
Samsung (ODM). It has standard Samsung specific IP blocks.
Regarding SoB, sorry I missed to add submitter's signoff. We will take
care in next patch series.

> 
> Best regards,
> Krzysztof

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Krzysztof Kozlowski]

On 21/07/2025 06:50, SeonGu Kang wrote:
> 2025-07-10 (목), 09:07 +0200, Krzysztof Kozlowski:
>> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
>>> From: SeonGu Kang <ksk4725@coasia.com>
>>>
>>> Add basic support for the Axis ARTPEC-8 SoC.
>>> This SoC contains four Cortex-A53 CPUs and other several IPs.
>>>
>>> Patches 1 to 10 provide the support for the clock controller,
>>> which is similar to other Samsung SoCs.
>>>
>> You should explain here (and in DTS patches or the bindings) the
>> hardware, that this is Samsung SoC.
>>
>> You could also explain the differences from Exynos and proposed
>> handling
>> of patches (because this is odd)
>>
>> Also, entire patchset has wrong and incomplete SoBs. Your SoB is
>> missing
>> everywhere, others have wrong order.
>>
>> Please read submitting patches first.
>>
> 
> This Custom SoC is owned by the Axis (OEM) and manufactured by the
> Samsung (ODM). It has standard Samsung specific IP blocks.


It is designed by Samsung. It is Samsung SoC.

Anyway, don't explain to me, but in your patchset.


Best regards,
Krzysztof

RE: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Pankaj Dubey]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Monday, July 21, 2025 12:10 PM
> To: SeonGu Kang <ksk4725@coasia.com>; Jesper Nilsson
> <jesper.nilsson@axis.com>; Michael Turquette <mturquette@baylibre.com>;
> Stephen Boyd <sboyd@kernel.org>; Rob Herring <robh@kernel.org>;
> Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> <conor+dt@kernel.org>; Sylwester Nawrocki <s.nawrocki@samsung.com>;
> Chanwoo Choi <cw00.choi@samsung.com>; Alim Akhtar
> <alim.akhtar@samsung.com>; Linus Walleij <linus.walleij@linaro.org>;
> Tomasz Figa <tomasz.figa@gmail.com>; Catalin Marinas
> <catalin.marinas@arm.com>; Will Deacon <will@kernel.org>; Arnd Bergmann
> <arnd@arndb.de>
> Cc: kenkim <kenkim@coasia.com>; Jongshin Park <pjsin865@coasia.com>;
> GunWoo Kim <gwk1013@coasia.com>; HaGyeong Kim
> <hgkim05@coasia.com>; GyoungBo Min <mingyoungbo@coasia.com>;
> SungMin Park <smn1196@coasia.com>; Pankaj Dubey
> <pankaj.dubey@samsung.com>; Shradha Todi <shradha.t@samsung.com>;
> Ravi Patel <ravi.patel@samsung.com>; Inbaraj E <inbaraj.e@samsung.com>;
> Swathi K S <swathi.ks@samsung.com>; Hrishikesh
> <hrishikesh.d@samsung.com>; Dongjin Yang <dj76.yang@samsung.com>;
> Sang Min Kim <hypmean.kim@samsung.com>; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org;
> linux-arm-kernel@axis.com; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org; soc@lists.linux.dev
> Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC
> 
> On 21/07/2025 06:50, SeonGu Kang wrote:
> > 2025-07-10 (목), 09:07 +0200, Krzysztof Kozlowski:
> >> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> >>> From: SeonGu Kang <ksk4725@coasia.com>
> >>>
> >>> Add basic support for the Axis ARTPEC-8 SoC.
> >>> This SoC contains four Cortex-A53 CPUs and other several IPs.
> >>>
> >>> Patches 1 to 10 provide the support for the clock controller, which
> >>> is similar to other Samsung SoCs.
> >>>
> >> You should explain here (and in DTS patches or the bindings) the
> >> hardware, that this is Samsung SoC.
> >>
> >> You could also explain the differences from Exynos and proposed
> >> handling of patches (because this is odd)
> >>
> >> Also, entire patchset has wrong and incomplete SoBs. Your SoB is
> >> missing everywhere, others have wrong order.
> >>
> >> Please read submitting patches first.
> >>
> >
> > This Custom SoC is owned by the Axis (OEM) and manufactured by the
> > Samsung (ODM). It has standard Samsung specific IP blocks.
> 
> 
> It is designed by Samsung. It is Samsung SoC.
> 
> Anyway, don't explain to me, but in your patchset.

Hi Krzysztof,

Thank you for your review comments on the ARTPEC-8 platform patches.
I'd like to add more context about the ARTPEC-8 SoC to help clarify its
relationship with Exynos.

Here are the key details about ARTPEC-8:
   - Manufactured by Samsung Foundry
   - SoC architecture is owned by Axis Communications
	- On similar model as Tesla's FSD chip owned by Tesla and 
              manufactured and  by Samsung
   - IPs from both Samsung and Axis Communications

Samsung-provided IPs:
  - UART
  - Ethernet (Vendor: Synopsys)
       - Same IP has been integrated as integrated in FSD Chip
  - SDIO
  - SPI
  - HSI2C
  - I2S
  - CMU (Clock Management Unit)
       Follows same CMU HW architecture as Exynos SoC have
  - Pinctrl (GPIO)
  - PCIe (Vendor: Synopsys)
       Though Exynos, FSD, ARTPEC have same DesignWare Controller, 
       the glue/wrapper layer around DWC Core has differences across
       these SoCs. All manufactured by Samsung, but differences are there
       in HW design and for different products. For the same reason PCIe patch
       refactoring effort is being put by us [1] to streamline single Exynos driver
       which can support all Samsung manufactured SoCs having DWC PCIe controller.
      [1]: https://patchwork.ozlabs.org/project/linux-pci/patch/20250625165229.3458-2-shradha.t@samsung.com/

Axis-provided IPs:
    - VIP (Image Sensor Processing IP)
    - VPP (Video Post Processing)
    - GPU
    - CDC (Video Encoder)

As part of the upstreaming effort, Samsung and Coasia (DSP) team will work together
to upstream basic SoC support and Samsung IPs support.
The Axis team will be the primary maintainer for the ARTPEC-8 SoC codebase.

Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe it's reasonable
to create a separate directory for it, similar to FSD.

We will remove Samsung and Coasia teams from the maintainers list in v2 and only
Axis team will be maintainer.

Maintainer list for previous generation of Axis chips (ARM based) is already present,
so this will be merged into that.

Please let us know if this explanation addresses your concerns. 
We'll update the commit message and cover letter accordingly.

Thanks,
Pankaj Dubey

> 
> Best regards,
> Krzysztof

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Krzysztof Kozlowski]

On 06/08/2025 10:22, Pankaj Dubey wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: Monday, July 21, 2025 12:10 PM
>> To: SeonGu Kang <ksk4725@coasia.com>; Jesper Nilsson
>> <jesper.nilsson@axis.com>; Michael Turquette <mturquette@baylibre.com>;
>> Stephen Boyd <sboyd@kernel.org>; Rob Herring <robh@kernel.org>;
>> Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
>> <conor+dt@kernel.org>; Sylwester Nawrocki <s.nawrocki@samsung.com>;
>> Chanwoo Choi <cw00.choi@samsung.com>; Alim Akhtar
>> <alim.akhtar@samsung.com>; Linus Walleij <linus.walleij@linaro.org>;
>> Tomasz Figa <tomasz.figa@gmail.com>; Catalin Marinas
>> <catalin.marinas@arm.com>; Will Deacon <will@kernel.org>; Arnd Bergmann
>> <arnd@arndb.de>
>> Cc: kenkim <kenkim@coasia.com>; Jongshin Park <pjsin865@coasia.com>;
>> GunWoo Kim <gwk1013@coasia.com>; HaGyeong Kim
>> <hgkim05@coasia.com>; GyoungBo Min <mingyoungbo@coasia.com>;
>> SungMin Park <smn1196@coasia.com>; Pankaj Dubey
>> <pankaj.dubey@samsung.com>; Shradha Todi <shradha.t@samsung.com>;
>> Ravi Patel <ravi.patel@samsung.com>; Inbaraj E <inbaraj.e@samsung.com>;
>> Swathi K S <swathi.ks@samsung.com>; Hrishikesh
>> <hrishikesh.d@samsung.com>; Dongjin Yang <dj76.yang@samsung.com>;
>> Sang Min Kim <hypmean.kim@samsung.com>; linux-kernel@vger.kernel.org;
>> linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org;
>> linux-arm-kernel@axis.com; linux-clk@vger.kernel.org;
>> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org; soc@lists.linux.dev
>> Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC
>>
>> On 21/07/2025 06:50, SeonGu Kang wrote:
>>> 2025-07-10 (목), 09:07 +0200, Krzysztof Kozlowski:
>>>> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
>>>>> From: SeonGu Kang <ksk4725@coasia.com>
>>>>>
>>>>> Add basic support for the Axis ARTPEC-8 SoC.
>>>>> This SoC contains four Cortex-A53 CPUs and other several IPs.
>>>>>
>>>>> Patches 1 to 10 provide the support for the clock controller, which
>>>>> is similar to other Samsung SoCs.
>>>>>
>>>> You should explain here (and in DTS patches or the bindings) the
>>>> hardware, that this is Samsung SoC.
>>>>
>>>> You could also explain the differences from Exynos and proposed
>>>> handling of patches (because this is odd)
>>>>
>>>> Also, entire patchset has wrong and incomplete SoBs. Your SoB is
>>>> missing everywhere, others have wrong order.
>>>>
>>>> Please read submitting patches first.
>>>>
>>>
>>> This Custom SoC is owned by the Axis (OEM) and manufactured by the
>>> Samsung (ODM). It has standard Samsung specific IP blocks.
>>
>>
>> It is designed by Samsung. It is Samsung SoC.
>>
>> Anyway, don't explain to me, but in your patchset.
> 
> Hi Krzysztof,
> 
> Thank you for your review comments on the ARTPEC-8 platform patches.
> I'd like to add more context about the ARTPEC-8 SoC to help clarify its
> relationship with Exynos.
> 
> Here are the key details about ARTPEC-8:
>    - Manufactured by Samsung Foundry
>    - SoC architecture is owned by Axis Communications
> 	- On similar model as Tesla's FSD chip owned by Tesla and 
>               manufactured and  by Samsung
>    - IPs from both Samsung and Axis Communications
> 
> Samsung-provided IPs:
>   - UART
>   - Ethernet (Vendor: Synopsys)
>        - Same IP has been integrated as integrated in FSD Chip
>   - SDIO
>   - SPI
>   - HSI2C
>   - I2S
>   - CMU (Clock Management Unit)
>        Follows same CMU HW architecture as Exynos SoC have
>   - Pinctrl (GPIO)
>   - PCIe (Vendor: Synopsys)
>        Though Exynos, FSD, ARTPEC have same DesignWare Controller, 
>        the glue/wrapper layer around DWC Core has differences across
>        these SoCs. All manufactured by Samsung, but differences are there
>        in HW design and for different products. For the same reason PCIe patch
>        refactoring effort is being put by us [1] to streamline single Exynos driver
>        which can support all Samsung manufactured SoCs having DWC PCIe controller.
>       [1]: https://patchwork.ozlabs.org/project/linux-pci/patch/20250625165229.3458-2-shradha.t@samsung.com/

So entire base of the SoC is Samsung.

> 
> Axis-provided IPs:
>     - VIP (Image Sensor Processing IP)
>     - VPP (Video Post Processing)
>     - GPU
>     - CDC (Video Encoder)
> 
> As part of the upstreaming effort, Samsung and Coasia (DSP) team will work together
> to upstream basic SoC support and Samsung IPs support.
> The Axis team will be the primary maintainer for the ARTPEC-8 SoC codebase.

Don't know what do you mean by "primary", but I want to be clear: this
classifies as Samsung SoC, so I will be maintaining and overlooking it
just like I maintain and take care about all Samsung SoCs. Otherwise you
will be introducing errors and warnings or, in best case different
style. And this already happened if I did not object!

Also SAME strict DT compliance profile will be applied. (see more on
that below)

> 
> Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe it's reasonable
> to create a separate directory for it, similar to FSD.

No. It was a mistake for FSD to keep it separate why? Because there is
no single non-Samsung stuff there. I am afraid exactly the same will
happen there.

Based on above list of blocks this should be done like Google is done,
so it goes as subdirectory of samsung (exynos). Can be called axis or
artpec-8.

To clarify: Only this SoC, not others which are not Samsung.

> 
> We will remove Samsung and Coasia teams from the maintainers list in v2 and only
> Axis team will be maintainer.

A bit unexpected or rather: just use names of people who WILL be
maintaining it. If this is Jesper and Lars, great. Just don't add
entries just because they are managers.

> 
> Maintainer list for previous generation of Axis chips (ARM based) is already present,
> so this will be merged into that.

Existing Artpec entry does not have tree mentioned, so if you choose
above, you must not add the tree, since the tree is provided by Samsung SoC.

OTOH, how are you going to add there strict DT compliance? Existing axis
is not following this, but artpec-8, as a Samsung derivative, MUST
FOLLOW strict DT compliance. And this should be clearly marked in
maintainer entry, just like everywhere else.


> 
> Please let us know if this explanation addresses your concerns. 
> We'll update the commit message and cover letter accordingly.


Best regards,
Krzysztof

RE: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Pankaj Dubey]

> Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC
> 
> On 06/08/2025 10:22, Pankaj Dubey wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: Monday, July 21, 2025 12:10 PM
> >> To: SeonGu Kang <ksk4725@coasia.com>; Jesper Nilsson
> >> <jesper.nilsson@axis.com>; Michael Turquette
> <mturquette@baylibre.com>;
> >> Stephen Boyd <sboyd@kernel.org>; Rob Herring <robh@kernel.org>;
> >> Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> >> <conor+dt@kernel.org>; Sylwester Nawrocki
> <s.nawrocki@samsung.com>;
> >> Chanwoo Choi <cw00.choi@samsung.com>; Alim Akhtar
> >> <alim.akhtar@samsung.com>; Linus Walleij <linus.walleij@linaro.org>;
> >> Tomasz Figa <tomasz.figa@gmail.com>; Catalin Marinas
> >> <catalin.marinas@arm.com>; Will Deacon <will@kernel.org>; Arnd
> Bergmann
> >> <arnd@arndb.de>
> >> Cc: kenkim <kenkim@coasia.com>; Jongshin Park <pjsin865@coasia.com>;
> >> GunWoo Kim <gwk1013@coasia.com>; HaGyeong Kim
> >> <hgkim05@coasia.com>; GyoungBo Min <mingyoungbo@coasia.com>;
> >> SungMin Park <smn1196@coasia.com>; Pankaj Dubey
> >> <pankaj.dubey@samsung.com>; Shradha Todi
> <shradha.t@samsung.com>;
> >> Ravi Patel <ravi.patel@samsung.com>; Inbaraj E
> <inbaraj.e@samsung.com>;
> >> Swathi K S <swathi.ks@samsung.com>; Hrishikesh
> >> <hrishikesh.d@samsung.com>; Dongjin Yang <dj76.yang@samsung.com>;
> >> Sang Min Kim <hypmean.kim@samsung.com>; linux-
> kernel@vger.kernel.org;
> >> linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org;
> >> linux-arm-kernel@axis.com; linux-clk@vger.kernel.org;
> >> devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;
> soc@lists.linux.dev
> >> Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC
> >>
> >> On 21/07/2025 06:50, SeonGu Kang wrote:
> >>> 2025-07-10 (목), 09:07 +0200, Krzysztof Kozlowski:
> >>>> On 10/07/2025 02:20, ksk4725@coasia.com wrote:
> >>>>> From: SeonGu Kang <ksk4725@coasia.com>
> >>>>>
> >>>>> Add basic support for the Axis ARTPEC-8 SoC.
> >>>>> This SoC contains four Cortex-A53 CPUs and other several IPs.
> >>>>>
> >>>>> Patches 1 to 10 provide the support for the clock controller, which
> >>>>> is similar to other Samsung SoCs.
> >>>>>
> >>>> You should explain here (and in DTS patches or the bindings) the
> >>>> hardware, that this is Samsung SoC.
> >>>>
> >>>> You could also explain the differences from Exynos and proposed
> >>>> handling of patches (because this is odd)
> >>>>
> >>>> Also, entire patchset has wrong and incomplete SoBs. Your SoB is
> >>>> missing everywhere, others have wrong order.
> >>>>
> >>>> Please read submitting patches first.
> >>>>
> >>>
> >>> This Custom SoC is owned by the Axis (OEM) and manufactured by the
> >>> Samsung (ODM). It has standard Samsung specific IP blocks.
> >>
> >>
> >> It is designed by Samsung. It is Samsung SoC.
> >>
> >> Anyway, don't explain to me, but in your patchset.
> >
> > Hi Krzysztof,
> >
> > Thank you for your review comments on the ARTPEC-8 platform patches.
> > I'd like to add more context about the ARTPEC-8 SoC to help clarify its
> > relationship with Exynos.
> >
> > Here are the key details about ARTPEC-8:
> >    - Manufactured by Samsung Foundry
> >    - SoC architecture is owned by Axis Communications
> > 	- On similar model as Tesla's FSD chip owned by Tesla and
> >               manufactured and  by Samsung
> >    - IPs from both Samsung and Axis Communications
> >
> > Samsung-provided IPs:
> >   - UART
> >   - Ethernet (Vendor: Synopsys)
> >        - Same IP has been integrated as integrated in FSD Chip
> >   - SDIO
> >   - SPI
> >   - HSI2C
> >   - I2S
> >   - CMU (Clock Management Unit)
> >        Follows same CMU HW architecture as Exynos SoC have
> >   - Pinctrl (GPIO)
> >   - PCIe (Vendor: Synopsys)
> >        Though Exynos, FSD, ARTPEC have same DesignWare Controller,
> >        the glue/wrapper layer around DWC Core has differences across
> >        these SoCs. All manufactured by Samsung, but differences are there
> >        in HW design and for different products. For the same reason PCIe
> patch
> >        refactoring effort is being put by us [1] to streamline single Exynos
> driver
> >        which can support all Samsung manufactured SoCs having DWC PCIe
> controller.
> >       [1]: https://protect2.fireeye.com/v1/url?k=8a8233e4-d5190ae8-
> 8a83b8ab-000babff3563-7bd7c9980190e0e8&q=1&e=2e04cfd4-33cf-4f00-
> a970-
> 7dcbf1d780ec&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Flinu
> x-pci%2Fpatch%2F20250625165229.3458-2-shradha.t%40samsung.com%2F
> 
> So entire base of the SoC is Samsung.

Yes, if we are saying this based on the core IPs (CMU, Pinctrl) and the fact that
it is manufactured by Samsung.

> 
> >
> > Axis-provided IPs:
> >     - VIP (Image Sensor Processing IP)
> >     - VPP (Video Post Processing)
> >     - GPU
> >     - CDC (Video Encoder)
> >
> > As part of the upstreaming effort, Samsung and Coasia (DSP) team will
> work together
> > to upstream basic SoC support and Samsung IPs support.
> > The Axis team will be the primary maintainer for the ARTPEC-8 SoC
> codebase.
> 
> Don't know what do you mean by "primary", but I want to be clear: this
> classifies as Samsung SoC, so I will be maintaining and overlooking it
> just like I maintain and take care about all Samsung SoCs. Otherwise you
> will be introducing errors and warnings or, in best case different
> style. And this already happened if I did not object!
> 

By "primary" I mean as it is product of Axis, and only Axis will be having access
to this SoCs in future they will be responsible to maintain it and add support for.

> Also SAME strict DT compliance profile will be applied. (see more on
> that below)
> 
> >
> > Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe it's
> reasonable
> > to create a separate directory for it, similar to FSD.
> 
> No. It was a mistake for FSD to keep it separate why? Because there is
> no single non-Samsung stuff there. I am afraid exactly the same will
> happen there.
> 

I am not sure, why you are saying this as a mistake, in case next version of FSD
or ARTPEC is manufactured (ODM) by another vendor in that case, won't it
create problems? 

For example ARTPEC-6/7 (ARM based) have their own directories as "arch/arm/boot/dts/axis/"
These were not Samsung (ODM) manufactures SoCs. 

But ARTPEC-8/9 (ARM64) based SoCs are samsung manufactured. What if the next version say
ARTPEC-10 is not samsung manufactured, so different version of products (SoCs) from
same vendor (OEM), in this case Axis, will have code in separate directories and with different maintainers? 

> Based on above list of blocks this should be done like Google is done,
> so it goes as subdirectory of samsung (exynos). Can be called axis or
> artpec-8.

I will suggest to keep axis, knowing the fact that sooner after artpec-8 patches gets approved and merged
we have plan to upstream artpec-9 (ARM64, Samsung manufactured) as well.

> 
> To clarify: Only this SoC, not others which are not Samsung.
> 
> >
> > We will remove Samsung and Coasia teams from the maintainers list in v2
> and only
> > Axis team will be maintainer.
> 
> A bit unexpected or rather: just use names of people who WILL be
> maintaining it. If this is Jesper and Lars, great. Just don't add
> entries just because they are managers.

AFAIK, Jesper will be taking care. 

> 
> >
> > Maintainer list for previous generation of Axis chips (ARM based) is already
> present,
> > so this will be merged into that.
> 
> Existing Artpec entry does not have tree mentioned, so if you choose
> above, you must not add the tree, since the tree is provided by Samsung SoC.
> 

OK

> OTOH, how are you going to add there strict DT compliance? Existing axis
> is not following this, but artpec-8, as a Samsung derivative, MUST
> FOLLOW strict DT compliance. And this should be clearly marked in
> maintainer entry, just like everywhere else.
>

As I said this is tricky situation, though artpec-8 is derivative of samsung, we can't confirm 
if future versions (> 9) will be samsung derivative. 

But this would be case for all such custom ASIC manufactured by samsung, so I would like to
understand how this will be handled? 

> 
> >
> > Please let us know if this explanation addresses your concerns.
> > We'll update the commit message and cover letter accordingly.
> 
> 
> Best regards,
> Krzysztof

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Krzysztof Kozlowski]

On 06/08/2025 11:05, Pankaj Dubey wrote:
> 
>> Also SAME strict DT compliance profile will be applied. (see more on
>> that below)
>>
>>>
>>> Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe it's
>> reasonable
>>> to create a separate directory for it, similar to FSD.
>>
>> No. It was a mistake for FSD to keep it separate why? Because there is
>> no single non-Samsung stuff there. I am afraid exactly the same will
>> happen there.
>>
> 
> I am not sure, why you are saying this as a mistake, in case next version of FSD


My mistake that I agreed on that, based on promise that "there will be
non Samsung stuff" and that "non Samsung stuff" never happened.

> or ARTPEC is manufactured (ODM) by another vendor in that case, won't it
> create problems? 


No problems here. Non-Samsung Artpec/Axis soc will not go there. It will
go the top-level axis directory, just like artpec-6


> 
> For example ARTPEC-6/7 (ARM based) have their own directories as "arch/arm/boot/dts/axis/"
> These were not Samsung (ODM) manufactures SoCs. 
> 
> But ARTPEC-8/9 (ARM64) based SoCs are samsung manufactured. What if the next version say
> ARTPEC-10 is not samsung manufactured, so different version of products (SoCs) from
> same vendor (OEM), in this case Axis, will have code in separate directories and with different maintainers? 

It will be the same with Google Pixel for whatever they decide in the
future. dts/exynos/google/ + dts/google/.

I know that this is not ideal, but for me grouping samsung stuff
together is far more important, because there is much, much more to
share between two SoCs designed by Samsung, than Axis-9 and future
non-Samsung Axis-10. And I have `git grep` as argument:
git grep compatible -- arch/arm64/boot/dts/tesla/

and point me to any Tesla IP. Zero results.


> 
>> Based on above list of blocks this should be done like Google is done,
>> so it goes as subdirectory of samsung (exynos). Can be called axis or
>> artpec-8.
> 
> I will suggest to keep axis, knowing the fact that sooner after artpec-8 patches gets approved and merged
> we have plan to upstream artpec-9 (ARM64, Samsung manufactured) as well.
> 
>>
>> To clarify: Only this SoC, not others which are not Samsung.
>>
>>>
>>> We will remove Samsung and Coasia teams from the maintainers list in v2
>> and only
>>> Axis team will be maintainer.
>>
>> A bit unexpected or rather: just use names of people who WILL be
>> maintaining it. If this is Jesper and Lars, great. Just don't add
>> entries just because they are managers.
> 
> AFAIK, Jesper will be taking care. 
> 
>>
>>>
>>> Maintainer list for previous generation of Axis chips (ARM based) is already
>> present,
>>> so this will be merged into that.
>>
>> Existing Artpec entry does not have tree mentioned, so if you choose
>> above, you must not add the tree, since the tree is provided by Samsung SoC.
>>
> 
> OK
> 
>> OTOH, how are you going to add there strict DT compliance? Existing axis
>> is not following this, but artpec-8, as a Samsung derivative, MUST
>> FOLLOW strict DT compliance. And this should be clearly marked in
>> maintainer entry, just like everywhere else.
>>
> 
> As I said this is tricky situation, though artpec-8 is derivative of samsung, we can't confirm 
> if future versions (> 9) will be samsung derivative. 
> 
> But this would be case for all such custom ASIC manufactured by samsung, so I would like to
> understand how this will be handled? 


I suggest to do the same as Google and when I say Google in this email,
I mean Pixel/GS101. Google was easier because there was no prior entry
and Axis has, so you will have two Axis entries. But I don't see how we
can add clean-dts profiles to the existing Axis entry, if you decide to
include Artpec-8 in that one.


Best regards,
Krzysztof

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Arnd Bergmann]

On Wed, Aug 6, 2025, at 11:23, Krzysztof Kozlowski wrote:
> On 06/08/2025 11:05, Pankaj Dubey wrote:
>> 
>> or ARTPEC is manufactured (ODM) by another vendor in that case, won't it
>> create problems? 
>
>
> No problems here. Non-Samsung Artpec/Axis soc will not go there. It will
> go the top-level axis directory, just like artpec-6

Agreed. We did have a case where something gradually changed
instead of changing ODMs entirely:

Apple A4 was mostly an Exynos-family chip but A18 is not.
If Axis turns into the next Apple and ARTPEC-23 is far enough
removed from ARTPEC-9 to no longer fit into the same family
as Exynos/Tensor/FSD, we can still reconsider the decision
in a decade.

     Arnd

RE: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Pankaj Dubey]

> Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC
> 
> On 06/08/2025 11:05, Pankaj Dubey wrote:
> >
> >> Also SAME strict DT compliance profile will be applied. (see more on
> >> that below)
> >>
> >>>
> >>> Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe
> it's
> >> reasonable
> >>> to create a separate directory for it, similar to FSD.
> >>
> >> No. It was a mistake for FSD to keep it separate why? Because there is
> >> no single non-Samsung stuff there. I am afraid exactly the same will
> >> happen there.
> >>
> >
> > I am not sure, why you are saying this as a mistake, in case next version of
> FSD
> 
> 
> My mistake that I agreed on that, based on promise that "there will be
> non Samsung stuff" and that "non Samsung stuff" never happened.
> 

I am not authorized to comment on FSD's non Samsung stuff at this moment.
But I got your point.

> > or ARTPEC is manufactured (ODM) by another vendor in that case, won't it
> > create problems?
> 
> 
> No problems here. Non-Samsung Artpec/Axis soc will not go there. It will
> go the top-level axis directory, just like artpec-6
> 

Okay, understood. I assume Axis team will be fine with this approach.
Let me align with them internally and address all the review comments in v2. 

> 
> >
> > For example ARTPEC-6/7 (ARM based) have their own directories as
> "arch/arm/boot/dts/axis/"
> > These were not Samsung (ODM) manufactures SoCs.
> >
> > But ARTPEC-8/9 (ARM64) based SoCs are samsung manufactured. What if
> the next version say
> > ARTPEC-10 is not samsung manufactured, so different version of products
> (SoCs) from
> > same vendor (OEM), in this case Axis, will have code in separate directories
> and with different maintainers?
> 
> It will be the same with Google Pixel for whatever they decide in the
> future. dts/exynos/google/ + dts/google/.
> 
> I know that this is not ideal, but for me grouping samsung stuff
> together is far more important, because there is much, much more to
> share between two SoCs designed by Samsung, than Axis-9 and future
> non-Samsung Axis-10. And I have `git grep` as argument:
> git grep compatible -- arch/arm64/boot/dts/tesla/
> 
> and point me to any Tesla IP. Zero results.
> 
> 
> >
> >> Based on above list of blocks this should be done like Google is done,
> >> so it goes as subdirectory of samsung (exynos). Can be called axis or
> >> artpec-8.
> >
> > I will suggest to keep axis, knowing the fact that sooner after artpec-8
> patches gets approved and merged
> > we have plan to upstream artpec-9 (ARM64, Samsung manufactured) as
> well.
> >
> >>
> >> To clarify: Only this SoC, not others which are not Samsung.
> >>
> >>>
> >>> We will remove Samsung and Coasia teams from the maintainers list in
> v2
> >> and only
> >>> Axis team will be maintainer.
> >>
> >> A bit unexpected or rather: just use names of people who WILL be
> >> maintaining it. If this is Jesper and Lars, great. Just don't add
> >> entries just because they are managers.
> >
> > AFAIK, Jesper will be taking care.
> >
> >>
> >>>
> >>> Maintainer list for previous generation of Axis chips (ARM based) is
> already
> >> present,
> >>> so this will be merged into that.
> >>
> >> Existing Artpec entry does not have tree mentioned, so if you choose
> >> above, you must not add the tree, since the tree is provided by Samsung
> SoC.
> >>
> >
> > OK
> >
> >> OTOH, how are you going to add there strict DT compliance? Existing axis
> >> is not following this, but artpec-8, as a Samsung derivative, MUST
> >> FOLLOW strict DT compliance. And this should be clearly marked in
> >> maintainer entry, just like everywhere else.
> >>
> >
> > As I said this is tricky situation, though artpec-8 is derivative of samsung, we
> can't confirm
> > if future versions (> 9) will be samsung derivative.
> >
> > But this would be case for all such custom ASIC manufactured by samsung,
> so I would like to
> > understand how this will be handled?
> 
> 
> I suggest to do the same as Google and when I say Google in this email,
> I mean Pixel/GS101. Google was easier because there was no prior entry
> and Axis has, so you will have two Axis entries. But I don't see how we
> can add clean-dts profiles to the existing Axis entry, if you decide to
> include Artpec-8 in that one.
> 

Okay we will have separate dts profile aligned with Exynos DT compliance for
ARM64 based Axis SoCs which are manufactured by Samsung at this moment. 

> 
> Best regards,
> Krzysztof

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

['Jesper Nilsson']

On Thu, Aug 07, 2025 at 12:26:27PM +0530, Pankaj Dubey wrote
> > Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC
> > On 06/08/2025 11:05, Pankaj Dubey wrote:
> > > or ARTPEC is manufactured (ODM) by another vendor in that case, won't it
> > > create problems?
> >
> >
> > No problems here. Non-Samsung Artpec/Axis soc will not go there. It will
> > go the top-level axis directory, just like artpec-6
> >
> 
> Okay, understood. I assume Axis team will be fine with this approach.
> Let me align with them internally and address all the review comments in v2.

Just for the record, Axis has no problem in having the ARTPEC-8 / ARTPEC-9
in the Samsung directory, while the older ARTPEC-6 / ARTPEC-7 and
any other future chips will be separate.

/^JN - Jesper Nilsson
-- 
               Jesper Nilsson -- jesper.nilsson@axis.com

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Linus Walleij]

Hi Hakyeong,

thanks for your patch!

On Thu, Jul 10, 2025 at 2:20 AM <ksk4725@coasia.com> wrote:

> Add basic support for the Axis ARTPEC-8 SoC.
> This SoC contains four Cortex-A53 CPUs and other several IPs.
>
> Patches 1 to 10 provide the support for the clock controller,
> which is similar to other Samsung SoCs.
>
> The remaining patches provide pinctrl support and
> initial device tree support.
>
> Hakyeong Kim (9):
>   dt-bindings: clock: Add ARTPEC-8 CMU bindings
>   clk: samsung: Add clock PLL support for ARTPEC-8 SoC
>   clk: samsung: artpec-8: Add initial clock support
>   clk: samsung: artpec-8: Add clock support for CMU_CMU block
>   clk: samsung: artpec-8: Add clock support for CMU_BUS block
>   clk: samsung: artpec-8: Add clock support for CMU_CORE block
>   clk: samsung: artpec-8: Add clock support for CMU_CPUCL block
>   clk: samsung: artpec-8: Add clock support for CMU_FSYS block
>   clk: samsung: artpec-8: Add clock support for CMU_PERI block

Out of the 9 patches there are 7 patches related to "CMU" without
any explanation or even expansion of this acronym.

Camera Management Unit? I think I'm not supposed to
guess. Is is an Axis-custom piece of hardware? (Would make
sense.)

Please expand this acronym and state clearly that (if this
is a correct assumption) that you are not supplying any
bindings and even less a driver for the "CMU" thing, just the
clocks. (That's fine the actual CMU can come later, but
it should be clear *what* it is.)

Yours,
Linus Walleij

Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

[Hakyeong Kim]

On Sat, 2025-07-12 at 21:26 +0200, Linus Walleij wrote:
> Hi Hakyeong,
> 
> thanks for your patch!
> 
> On Thu, Jul 10, 2025 at 2:20 AM <ksk4725@coasia.com> wrote:
> 
> > Add basic support for the Axis ARTPEC-8 SoC.
> > This SoC contains four Cortex-A53 CPUs and other several IPs.
> > 
> > Patches 1 to 10 provide the support for the clock controller,
> > which is similar to other Samsung SoCs.
> > 
> > The remaining patches provide pinctrl support and
> > initial device tree support.
> > 
> > Hakyeong Kim (9):
> >   dt-bindings: clock: Add ARTPEC-8 CMU bindings
> >   clk: samsung: Add clock PLL support for ARTPEC-8 SoC
> >   clk: samsung: artpec-8: Add initial clock support
> >   clk: samsung: artpec-8: Add clock support for CMU_CMU block
> >   clk: samsung: artpec-8: Add clock support for CMU_BUS block
> >   clk: samsung: artpec-8: Add clock support for CMU_CORE block
> >   clk: samsung: artpec-8: Add clock support for CMU_CPUCL block
> >   clk: samsung: artpec-8: Add clock support for CMU_FSYS block
> >   clk: samsung: artpec-8: Add clock support for CMU_PERI block
> 
> Out of the 9 patches there are 7 patches related to "CMU" without
> any explanation or even expansion of this acronym.
> 
> Camera Management Unit? I think I'm not supposed to
> guess. Is is an Axis-custom piece of hardware? (Would make
> sense.)
> 
> Please expand this acronym and state clearly that (if this
> is a correct assumption) that you are not supplying any
> bindings and even less a driver for the "CMU" thing, just the
> clocks. (That's fine the actual CMU can come later, but
> it should be clear *what* it is.)

Ok, I will add CMU abbreviation on cover-letter and respective patches.

Thanks,
Hakyeong Kim

> 
> Yours,
> Linus Walleij

[PATCH v2 00/10] Add support for the Axis ARTPEC-8 SoC

[Ravi Patel]

Add basic support for the Axis ARTPEC-8 SoC which contains
quad-core Cortex-A53 CPU and other several IPs. This SoC is an
Axis-designed chipset used in surveillance camera products such as
the AXIS Q1656-LE and AXIS Q3538-LVE.

This ARTPEC-8 SoC has a variety of Samsung-specific IP blocks and
Axis-specific IP blocks and SoC is manufactured by Samsung Foundry.

List of Samsung-provided IPs:
- UART
- Ethernet (Vendor: Synopsys)
- SDIO
- SPI
- HSI2C
- I2S
- CMU (Clock Management Unit)
- Pinctrl (GPIO)
- PCIe (Vendor: Synopsys)
- USB (Vendor: Synopsys)

List of Axis-provided IPs:
- VIP (Image Sensor Processing IP)
- VPP (Video Post Processing)
- GPU
- CDC (Video Encoder)

This patch series includes below changes:
- CMU (Clock Management Unit) driver and its bindings
- GPIO pinctrl configuration and its bindings
- Basic Device Tree for ARTPEC-8 SoC and boards

The patch series has been tested on the ARTPEC-8 EVB with
Linux v6.15-rc5 and intended to be merged via the `arm-soc` tree.

---
Changes in v2:
- Update SoB sections in all patches
- Update the copyright year to 2025
- Add CMU abbreviation description
- Merge dt-bindings patch 01 and 02 into single patch
- Modify yaml file to fit coding style in CMU
- Modify clock-names
- Reorder config macros to fit coding style
- Remove the unused macro in clock driver code
- Squash all clock driver patches (4 to 10) into single patch
- Split yaml conversion patch translation and add ARTPEC-8 SoC
- Remove "clock-frequency" property from cpu node in dtsi
- Remove the "status" property in dts and dtsi
- Reorder the DTS and pin nodes to follow the alphabetical and DTS coding style
- Change items property in axis.yaml
- Move dts files to exynos folder
- Removed ARCH_ARTPEC8 from platform Kconfig
- Add pattern in MAINTAINER file
- Merge dtsi and pinctrl dtsi file
- Split board dts file

Link to v1: https://lore.kernel.org/all/20250710002047.1573841-1-ksk4725@coasia.com/
NOTE: The first version has been sent by Coasia.
      After that, it has been agreed between Coasia and Samsung that Samsung will take
      ownership of upstreaming ARTPEC-8 and ARTPEC-9 platforms.
---

Hakyeong Kim (3):
  dt-bindings: clock: Add ARTPEC-8 clock controller
  clk: samsung: Add clock PLL support for ARTPEC-8 SoC
  clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC

Ravi Patel (1):
  dt-bindings: arm: Convert Axis board/soc bindings to json-schema

SeonGu Kang (3):
  dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC
  pinctrl: samsung: Add ARTPEC-8 SoC specific configuration
  arm64: dts: axis: Add ARTPEC-8 Grizzly dts support

SungMin Park (3):
  dt-bindings: arm: axis: Add ARTPEC-8 grizzly board
  arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support
  arm64: defconfig: Enable Axis ARTPEC SoC

 .../devicetree/bindings/arm/axis.txt          |   13 -
 .../devicetree/bindings/arm/axis.yaml         |   36 +
 .../bindings/clock/axis,artpec8-clock.yaml    |  213 ++++
 .../bindings/pinctrl/samsung,pinctrl.yaml     |    1 +
 MAINTAINERS                                   |   12 +
 arch/arm64/Kconfig.platforms                  |    7 +
 arch/arm64/boot/dts/exynos/Makefile           |    1 +
 arch/arm64/boot/dts/exynos/axis/Makefile      |    4 +
 .../boot/dts/exynos/axis/artpec-pinctrl.h     |   36 +
 .../boot/dts/exynos/axis/artpec8-grizzly.dts  |   35 +
 .../boot/dts/exynos/axis/artpec8-pinctrl.dtsi |  120 ++
 arch/arm64/boot/dts/exynos/axis/artpec8.dtsi  |  244 ++++
 arch/arm64/configs/defconfig                  |    1 +
 drivers/clk/samsung/Makefile                  |    1 +
 drivers/clk/samsung/clk-artpec8.c             | 1044 +++++++++++++++++
 drivers/clk/samsung/clk-pll.c                 |  128 +-
 drivers/clk/samsung/clk-pll.h                 |    2 +
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    |   50 +
 drivers/pinctrl/samsung/pinctrl-exynos.h      |   10 +
 drivers/pinctrl/samsung/pinctrl-samsung.c     |    2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |    1 +
 include/dt-bindings/clock/axis,artpec8-clk.h  |  169 +++
 22 files changed, 2116 insertions(+), 14 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt
 create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
 create mode 100644 arch/arm64/boot/dts/exynos/axis/Makefile
 create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
 create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts
 create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8.dtsi
 create mode 100644 drivers/clk/samsung/clk-artpec8.c
 create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h

--
2.49.0

[PATCH v2 01/10] dt-bindings: clock: Add ARTPEC-8 clock controller

[Ravi Patel]

From: Hakyeong Kim <hgkim05@coasia.com>

Add dt-schema for Axis ARTPEC-8 SoC clock controller.

The Clock Management Unit (CMU) has a top-level block CMU_CMU
which generates clocks for other blocks.

Add device-tree binding definitions for following CMU blocks:
- CMU_CMU
- CMU_BUS
- CMU_CORE
- CMU_CPUCL
- CMU_FSYS
- CMU_IMEM
- CMU_PERI

Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 .../bindings/clock/axis,artpec8-clock.yaml    | 213 ++++++++++++++++++
 include/dt-bindings/clock/axis,artpec8-clk.h  | 169 ++++++++++++++
 2 files changed, 382 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
 create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h

diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
new file mode 100644
index 000000000000..de923afb8dfe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axis ARTPEC-8 SoC clock controller
+
+maintainers:
+  - Jesper Nilsson <jesper.nilsson@axis.com>
+
+description: |
+  ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
+  units, generating clocks for different domains. Those CMU units are modeled
+  as separate device tree nodes, and might depend on each other.
+  The root clock in that root tree is an external clock: OSCCLK (25 MHz).
+  This external clock must be defined as a fixed-rate clock in dts.
+
+  CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other clocks of function blocks (other CMUs) are usually
+  derived from CMU_CMU.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'include/dt-bindings/clock/axis,artpec8-clk.h' header.
+
+properties:
+  compatible:
+    enum:
+      - axis,artpec8-cmu-cmu
+      - axis,artpec8-cmu-bus
+      - axis,artpec8-cmu-core
+      - axis,artpec8-cmu-cpucl
+      - axis,artpec8-cmu-fsys
+      - axis,artpec8-cmu-imem
+      - axis,artpec8-cmu-peri
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec8-cmu-cmu
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+
+        clock-names:
+          items:
+            - const: fin_pll
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec8-cmu-bus
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_BUS BUS clock (from CMU_CMU)
+            - description: CMU_BUS DLP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: bus
+            - const: dlp
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec8-cmu-core
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_CORE main clock (from CMU_CMU)
+            - description: CMU_CORE DLP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: main
+            - const: dlp
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec8-cmu-cpucl
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_CPUCL switch clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: switch
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec8-cmu-fsys
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_FSYS SCAN0 clock (from CMU_CMU)
+            - description: CMU_FSYS SCAN1 clock (from CMU_CMU)
+            - description: CMU_FSYS BUS clock (from CMU_CMU)
+            - description: CMU_FSYS IP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: scan0
+            - const: scan1
+            - const: bus
+            - const: ip
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec8-cmu-imem
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_IMEM ACLK clock (from CMU_CMU)
+            - description: CMU_IMEM JPEG clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: aclk
+            - const: jpeg
+
+  - if:
+      properties:
+        compatible:
+          const: axis,artpec8-cmu-peri
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (25 MHz)
+            - description: CMU_PERI IP clock (from CMU_CMU)
+            - description: CMU_PERI AUDIO clock (from CMU_CMU)
+            - description: CMU_PERI DISP clock (from CMU_CMU)
+
+        clock-names:
+          items:
+            - const: fin_pll
+            - const: ip
+            - const: audio
+            - const: disp
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_FSYS
+  - |
+    #include <dt-bindings/clock/axis,artpec8-clk.h>
+
+    cmu_fsys: clock-controller@16c10000 {
+        compatible = "axis,artpec8-cmu-fsys";
+        reg = <0x16c10000 0x4000>;
+        #clock-cells = <1>;
+        clocks = <&fin_pll>,
+                 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
+                 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
+                 <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
+                 <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
+        clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
+    };
+
+...
diff --git a/include/dt-bindings/clock/axis,artpec8-clk.h b/include/dt-bindings/clock/axis,artpec8-clk.h
new file mode 100644
index 000000000000..1e6e1409dd94
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec8-clk.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025 Axis Communications AB.
+ *             https://www.axis.com
+ *
+ * Device Tree binding constants for ARTPEC-8 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H
+#define _DT_BINDINGS_CLOCK_ARTPEC8_H
+
+/* CMU_CMU */
+#define CLK_FOUT_SHARED0_PLL					1
+#define CLK_DOUT_SHARED0_DIV2					2
+#define CLK_DOUT_SHARED0_DIV3					3
+#define CLK_DOUT_SHARED0_DIV4					4
+#define CLK_FOUT_SHARED1_PLL					5
+#define CLK_DOUT_SHARED1_DIV2					6
+#define CLK_DOUT_SHARED1_DIV3					7
+#define CLK_DOUT_SHARED1_DIV4					8
+#define CLK_FOUT_AUDIO_PLL					9
+#define CLK_DOUT_CMU_BUS					10
+#define CLK_DOUT_CMU_BUS_DLP					11
+#define CLK_DOUT_CMU_CDC_CORE					12
+#define CLK_DOUT_CMU_OTP					13
+#define CLK_DOUT_CMU_CORE_MAIN					14
+#define CLK_DOUT_CMU_CORE_DLP					15
+#define CLK_DOUT_CMU_CPUCL_SWITCH				16
+#define CLK_DOUT_CMU_DLP_CORE					17
+#define CLK_DOUT_CMU_FSYS_BUS					18
+#define CLK_DOUT_CMU_FSYS_IP					19
+#define CLK_DOUT_CMU_FSYS_SCAN0					20
+#define CLK_DOUT_CMU_FSYS_SCAN1					21
+#define CLK_DOUT_CMU_GPU_3D					22
+#define CLK_DOUT_CMU_GPU_2D					23
+#define CLK_DOUT_CMU_IMEM_ACLK					24
+#define CLK_DOUT_CMU_IMEM_JPEG					25
+#define CLK_DOUT_CMU_MIF_SWITCH					26
+#define CLK_DOUT_CMU_MIF_BUSP					27
+#define CLK_DOUT_CMU_PERI_DISP					28
+#define CLK_DOUT_CMU_PERI_IP					29
+#define CLK_DOUT_CMU_PERI_AUDIO					30
+#define CLK_DOUT_CMU_RSP_CORE					31
+#define CLK_DOUT_CMU_TRFM_CORE					32
+#define CLK_DOUT_CMU_VCA_ACE					33
+#define CLK_DOUT_CMU_VCA_OD					34
+#define CLK_DOUT_CMU_VIO_CORE					35
+#define CLK_DOUT_CMU_VIO_AUDIO					36
+#define CLK_DOUT_CMU_VIP0_CORE					37
+#define CLK_DOUT_CMU_VIP1_CORE					38
+#define CLK_DOUT_CMU_VPP_CORE					39
+
+/* CMU_BUS */
+#define CLK_MOUT_BUS_ACLK_USER					1
+#define CLK_MOUT_BUS_DLP_USER					2
+#define CLK_DOUT_BUS_PCLK					3
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_ACLK_USER					1
+#define CLK_MOUT_CORE_DLP_USER					2
+#define CLK_DOUT_CORE_PCLK					3
+
+/* CMU_CPUCL */
+#define CLK_FOUT_CPUCL_PLL					1
+#define CLK_MOUT_CPUCL_PLL					2
+#define CLK_MOUT_CPUCL_SWITCH_USER				3
+#define CLK_DOUT_CPUCL_CPU					4
+#define CLK_DOUT_CPUCL_CLUSTER_ACLK				5
+#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG				6
+#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK				7
+#define CLK_DOUT_CPUCL_CLUSTER_ATCLK				8
+#define CLK_DOUT_CPUCL_PCLK					9
+#define CLK_DOUT_CPUCL_CMUREF					10
+#define CLK_DOUT_CPUCL_DBG					11
+#define CLK_DOUT_CPUCL_PCLKDBG					12
+#define CLK_GOUT_CPUCL_CLUSTER_CPU				13
+#define CLK_GOUT_CPUCL_SHORTSTOP				14
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG			15
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK			16
+
+/* CMU_FSYS */
+#define CLK_FOUT_FSYS_PLL					1
+#define CLK_MOUT_FSYS_SCAN0_USER				2
+#define CLK_MOUT_FSYS_SCAN1_USER				3
+#define CLK_MOUT_FSYS_BUS_USER					4
+#define CLK_MOUT_FSYS_MMC_USER					5
+#define CLK_DOUT_FSYS_PCIE_PIPE					6
+#define CLK_DOUT_FSYS_ADC					7
+#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL			8
+#define CLK_DOUT_FSYS_EQOS_INT125				9
+#define CLK_DOUT_FSYS_OTP_MEM					10
+#define CLK_DOUT_FSYS_SCLK_UART					11
+#define CLK_DOUT_FSYS_EQOS_25					12
+#define CLK_DOUT_FSYS_EQOS_2p5					13
+#define CLK_DOUT_FSYS_BUS300					14
+#define CLK_DOUT_FSYS_BUS_QSPI					15
+#define CLK_DOUT_FSYS_MMC_CARD0					16
+#define CLK_DOUT_FSYS_MMC_CARD1					17
+#define CLK_DOUT_SCAN_CLK_FSYS_125				18
+#define CLK_DOUT_FSYS_QSPI					19
+#define CLK_DOUT_FSYS_SFMC_NAND					20
+#define CLK_DOUT_FSYS_SCAN_CLK_MMC				21
+#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20	22
+#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY		23
+#define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK			24
+#define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK			25
+#define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK			26
+#define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK			27
+#define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0			28
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG		29
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG		30
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG		31
+#define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK		32
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I			33
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I		34
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5	35
+#define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND		36
+#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN			37
+#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK			38
+#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN			39
+#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK			40
+#define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN			41
+#define CLK_GOUT_FSYS_UART0_PCLK				42
+#define CLK_GOUT_FSYS_UART0_SCLK_UART				43
+#define CLK_GOUT_FSYS_BUS_QSPI					44
+#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK			45
+#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK			46
+
+/* CMU_IMEM */
+#define CLK_MOUT_IMEM_ACLK_USER					1
+#define CLK_MOUT_IMEM_GIC_CA53					2
+#define CLK_MOUT_IMEM_GIC_CA5					3
+#define CLK_MOUT_IMEM_JPEG_USER					4
+#define CLK_GOUT_IMEM_MCT_PCLK					5
+#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF				6
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_IP_USER					1
+#define CLK_MOUT_PERI_AUDIO_USER				2
+#define CLK_MOUT_PERI_I2S0					3
+#define CLK_MOUT_PERI_I2S1					4
+#define CLK_MOUT_PERI_DISP_USER					5
+#define CLK_DOUT_PERI_SPI					6
+#define CLK_DOUT_PERI_UART1					7
+#define CLK_DOUT_PERI_UART2					8
+#define CLK_DOUT_PERI_PCLK					9
+#define CLK_DOUT_PERI_I2S0					10
+#define CLK_DOUT_PERI_I2S1					11
+#define CLK_DOUT_PERI_DSIM					12
+#define CLK_GOUT_PERI_UART1_PCLK				13
+#define CLK_GOUT_PERI_UART1_SCLK_UART				14
+#define CLK_GOUT_PERI_UART2_PCLK				15
+#define CLK_GOUT_PERI_UART2_SCLK_UART				16
+#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK			17
+#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK			18
+#define CLK_GOUT_PERI_SPI0_PCLK					19
+#define CLK_GOUT_PERI_SPI0_SCLK_SPI				20
+#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS		21
+#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST			22
+#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST			23
+#define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK			24
+#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK			25
+#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK			26
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK		27
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK		28
+
+#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */
--
2.49.0

Re: [PATCH v2 01/10] dt-bindings: clock: Add ARTPEC-8 clock controller

[Rob Herring (Arm)]

On Thu, 21 Aug 2025 18:02:45 +0530, Ravi Patel wrote:
> From: Hakyeong Kim <hgkim05@coasia.com>
> 
> Add dt-schema for Axis ARTPEC-8 SoC clock controller.
> 
> The Clock Management Unit (CMU) has a top-level block CMU_CMU
> which generates clocks for other blocks.
> 
> Add device-tree binding definitions for following CMU blocks:
> - CMU_CMU
> - CMU_BUS
> - CMU_CORE
> - CMU_CPUCL
> - CMU_FSYS
> - CMU_IMEM
> - CMU_PERI
> 
> Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
> Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> ---
>  .../bindings/clock/axis,artpec8-clock.yaml    | 213 ++++++++++++++++++
>  include/dt-bindings/clock/axis,artpec8-clk.h  | 169 ++++++++++++++
>  2 files changed, 382 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
>  create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v2 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC

[Ravi Patel]

From: Hakyeong Kim <hgkim05@coasia.com>

Add below clock PLL support for Axis ARTPEC-8 SoC platform:
- pll_1017x: Integer PLL with mid frequency FVCO (950 to 2400 MHz)
             This is used in ARTPEC-8 SoC for shared PLL

- pll_1031x: Integer/Fractional PLL with mid frequency FVCO
             (600 to 1200 MHz)
             This is used in ARTPEC-8 SoC for Audio PLL

FOUT calculation for pll_1017x and pll_1031x:
FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL
FOUT = (((MDIV + KDIV)/65536) x FIN)/(PDIV x 2^SDIV) for fractional PLL

Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 drivers/clk/samsung/clk-pll.c | 128 +++++++++++++++++++++++++++++++++-
 drivers/clk/samsung/clk-pll.h |   2 +
 2 files changed, 129 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index fe8abe442c51..614063396e23 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -273,7 +273,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	}
 
 	/* Set PLL lock time. */
-	if (pll->type == pll_142xx)
+	if (pll->type == pll_142xx || pll->type == pll_1017x)
 		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
 			pll->lock_reg);
 	else
@@ -1325,6 +1325,125 @@ static const struct clk_ops samsung_pll531x_clk_ops = {
 	.recalc_rate = samsung_pll531x_recalc_rate,
 };
 
+/*
+ * PLL1031x Clock Type
+ */
+#define PLL1031X_LOCK_FACTOR	(500)
+
+#define PLL1031X_MDIV_MASK	(0x3ff)
+#define PLL1031X_PDIV_MASK	(0x3f)
+#define PLL1031X_SDIV_MASK	(0x7)
+#define PLL1031X_MDIV_SHIFT	(16)
+#define PLL1031X_PDIV_SHIFT	(8)
+#define PLL1031X_SDIV_SHIFT	(0)
+
+#define PLL1031X_KDIV_MASK	(0xffff)
+#define PLL1031X_KDIV_SHIFT	(0)
+#define PLL1031X_MFR_MASK	(0x3f)
+#define PLL1031X_MRR_MASK	(0x1f)
+#define PLL1031X_MFR_SHIFT	(16)
+#define PLL1031X_MRR_SHIFT	(24)
+
+static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw,
+						  unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3;
+	u64 fvco = parent_rate;
+
+	pll_con0 = readl_relaxed(pll->con_reg);
+	pll_con3 = readl_relaxed(pll->con_reg + 0xc);
+	mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK;
+	kdiv = (pll_con3 & PLL1031X_KDIV_MASK);
+
+	fvco *= (mdiv << PLL1031X_MDIV_SHIFT) + kdiv;
+	do_div(fvco, (pdiv << sdiv));
+	fvco >>= PLL1031X_MDIV_SHIFT;
+
+	return (unsigned long)fvco;
+}
+
+static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3,
+					const struct samsung_pll_rate_table *rate)
+{
+	u32 old_mdiv, old_pdiv, old_kdiv;
+
+	old_mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
+	old_pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
+	old_kdiv = (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK;
+
+	return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv ||
+		old_kdiv != rate->kdiv);
+}
+
+static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drate,
+				     unsigned long prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	const struct samsung_pll_rate_table *rate;
+	u32 con0, con3;
+
+	/* Get required rate settings from table */
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+		       drate, clk_hw_get_name(hw));
+		return -EINVAL;
+	}
+
+	con0 = readl_relaxed(pll->con_reg);
+	con3 = readl_relaxed(pll->con_reg + 0xc);
+
+	if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) {
+		/* If only s change, change just s value only */
+		con0 &= ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT);
+		con0 |= rate->sdiv << PLL1031X_SDIV_SHIFT;
+		writel_relaxed(con0, pll->con_reg);
+
+		return 0;
+	}
+
+	/* Set PLL lock time. */
+	writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg);
+
+	/* Set PLL M, P, and S values. */
+	con0 &= ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) |
+		  (PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) |
+		  (PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT));
+
+	con0 |= (rate->mdiv << PLL1031X_MDIV_SHIFT) |
+		(rate->pdiv << PLL1031X_PDIV_SHIFT) |
+		(rate->sdiv << PLL1031X_SDIV_SHIFT);
+
+	/* Set PLL K, MFR and MRR values. */
+	con3 = readl_relaxed(pll->con_reg + 0xc);
+	con3 &= ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) |
+		  (PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) |
+		  (PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT));
+	con3 |= (rate->kdiv << PLL1031X_KDIV_SHIFT) |
+		(rate->mfr << PLL1031X_MFR_SHIFT) |
+		(rate->mrr << PLL1031X_MRR_SHIFT);
+
+	/* Write configuration to PLL */
+	writel_relaxed(con0, pll->con_reg);
+	writel_relaxed(con3, pll->con_reg + 0xc);
+
+	/* Wait for PLL lock if the PLL is enabled */
+	return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
+}
+
+static const struct clk_ops samsung_pll1031x_clk_ops = {
+	.recalc_rate = samsung_pll1031x_recalc_rate,
+	.round_rate = samsung_pll_round_rate,
+	.set_rate = samsung_pll1031x_set_rate,
+};
+
+static const struct clk_ops samsung_pll1031x_clk_min_ops = {
+	.recalc_rate = samsung_pll1031x_recalc_rate,
+};
+
 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 				const struct samsung_pll_clock *pll_clk)
 {
@@ -1373,6 +1492,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	case pll_1451x:
 	case pll_1452x:
 	case pll_142xx:
+	case pll_1017x:
 		pll->enable_offs = PLL35XX_ENABLE_SHIFT;
 		pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
 		if (!pll->rate_table)
@@ -1468,6 +1588,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	case pll_4311:
 		init.ops = &samsung_pll531x_clk_ops;
 		break;
+	case pll_1031x:
+		if (!pll->rate_table)
+			init.ops = &samsung_pll1031x_clk_min_ops;
+		else
+			init.ops = &samsung_pll1031x_clk_ops;
+		break;
 	default:
 		pr_warn("%s: Unknown pll type for pll clk %s\n",
 			__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index e9a5f8e0e0a3..6c8bb7f26da5 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -49,6 +49,8 @@ enum samsung_pll_type {
 	pll_0718x,
 	pll_0732x,
 	pll_4311,
+	pll_1017x,
+	pll_1031x,
 };
 
 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
-- 
2.49.0

Re: [PATCH v2 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC

[Krzysztof Kozlowski]

On 21/08/2025 14:32, Ravi Patel wrote:
> +
> +static const struct clk_ops samsung_pll1031x_clk_ops = {
> +	.recalc_rate = samsung_pll1031x_recalc_rate,
> +	.round_rate = samsung_pll_round_rate,


This will conflict with round_rate drop, so might need rebasing. Please
follow up discussion or decisions in the round rate patchset.

Best regards,
Krzysztof

RE: [PATCH v2 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC

[Ravi Patel]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 22 August 2025 12:02
> To: Ravi Patel <ravi.patel@samsung.com>; jesper.nilsson@axis.com; mturquette@baylibre.com; sboyd@kernel.org;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com;
> alim.akhtar@samsung.com; linus.walleij@linaro.org; tomasz.figa@gmail.com; catalin.marinas@arm.com; will@kernel.org;
> arnd@arndb.de
> Cc: ksk4725@coasia.com; kenkim@coasia.com; pjsin865@coasia.com; gwk1013@coasia.com; hgkim05@coasia.com;
> mingyoungbo@coasia.com; smn1196@coasia.com; pankaj.dubey@samsung.com; shradha.t@samsung.com;
> inbaraj.e@samsung.com; swathi.ks@samsung.com; hrishikesh.d@samsung.com; dj76.yang@samsung.com;
> hypmean.kim@samsung.com; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; linux-arm-kernel@axis.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> gpio@vger.kernel.org; soc@lists.linux.dev
> Subject: Re: [PATCH v2 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC
> 
> On 21/08/2025 14:32, Ravi Patel wrote:
> > +
> > +static const struct clk_ops samsung_pll1031x_clk_ops = {
> > +	.recalc_rate = samsung_pll1031x_recalc_rate,
> > +	.round_rate = samsung_pll_round_rate,
> 
> 
> This will conflict with round_rate drop, so might need rebasing. Please
> follow up discussion or decisions in the round rate patchset.

Thanks for review. Yes, I can see conflicts with below patch 
https://lore.kernel.org/linux-samsung-soc/20250811-clk-for-stephen-round-rate-v1-99-b3bf97b038dc@redhat.com/

Since merging strategy of round_rate patches are not clear as of now, will wait for couple of days before posting v3.
Request to review other patches also.

Thanks,
Ravi

> 
> Best regards,
> Krzysztof

[PATCH v2 03/10] clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC

[Ravi Patel]

From: Hakyeong Kim <hgkim05@coasia.com>

Add initial clock support for Axis ARTPEC-8 SoC which is required
for enabling basic clock management.

Add clock support for below CMU (Clock Management Unit) blocks
in ARTPEC-8 SoC:
 - CMU_CMU
 - CMU_BUS
 - CMU_CORE
 - CMU_CPUCL
 - CMU_FSYS
 - CMU_IMEM
 - CMU_PERI

Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 drivers/clk/samsung/Makefile      |    1 +
 drivers/clk/samsung/clk-artpec8.c | 1044 +++++++++++++++++++++++++++++
 2 files changed, 1045 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-artpec8.c

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b77fe288e4bb..ef464f434740 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_EXYNOS_5260_COMMON_CLK)	+= clk-exynos5260.o
 obj-$(CONFIG_EXYNOS_5410_COMMON_CLK)	+= clk-exynos5410.o
 obj-$(CONFIG_EXYNOS_5420_COMMON_CLK)	+= clk-exynos5420.o
 obj-$(CONFIG_EXYNOS_5420_COMMON_CLK)	+= clk-exynos5-subcmu.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-artpec8.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos5433.o
 obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
 obj-$(CONFIG_EXYNOS_CLKOUT)	+= clk-exynos-clkout.o
diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c
new file mode 100644
index 000000000000..0ea7c8b58674
--- /dev/null
+++ b/drivers/clk/samsung/clk-artpec8.c
@@ -0,0 +1,1044 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025 Axis Communications AB.
+ *             https://www.axis.com
+ *
+ * Common Clock Framework support for ARTPEC-8 SoC.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/axis,artpec8-clk.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CMU_CMU_NR_CLK				(CLK_DOUT_CMU_VPP_CORE + 1)
+#define CMU_BUS_NR_CLK				(CLK_DOUT_BUS_PCLK + 1)
+#define CMU_CORE_NR_CLK				(CLK_DOUT_CORE_PCLK + 1)
+#define CMU_CPUCL_NR_CLK			(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK + 1)
+#define CMU_FSYS_NR_CLK				(CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK + 1)
+#define CMU_IMEM_NR_CLK				(CLK_GOUT_IMEM_PCLK_TMU0_APBIF + 1)
+#define CMU_PERI_NR_CLK				(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK + 1)
+
+/* Register Offset definitions for CMU_CMU (0x12400000) */
+#define PLL_LOCKTIME_PLL_AUDIO				0x0000
+#define PLL_LOCKTIME_PLL_SHARED0			0x0004
+#define PLL_LOCKTIME_PLL_SHARED1			0x0008
+#define PLL_CON0_PLL_AUDIO				0x0100
+#define PLL_CON0_PLL_SHARED0				0x0120
+#define PLL_CON0_PLL_SHARED1				0x0140
+#define CLK_CON_MUX_CLKCMU_2D				0x1000
+#define CLK_CON_MUX_CLKCMU_3D				0x1004
+#define CLK_CON_MUX_CLKCMU_BUS				0x1008
+#define CLK_CON_MUX_CLKCMU_BUS_DLP			0x100c
+#define CLK_CON_MUX_CLKCMU_CDC_CORE			0x1010
+#define CLK_CON_MUX_CLKCMU_FSYS_SCAN0			0x1014
+#define CLK_CON_MUX_CLKCMU_FSYS_SCAN1			0x1018
+#define CLK_CON_MUX_CLKCMU_IMEM_JPEG			0x101c
+#define CLK_CON_MUX_CLKCMU_PERI_DISP			0x1020
+#define CLK_CON_MUX_CLKCMU_CORE_BUS			0x1024
+#define CLK_CON_MUX_CLKCMU_CORE_DLP			0x1028
+#define CLK_CON_MUX_CLKCMU_CPUCL_SWITCH			0x1030
+#define CLK_CON_MUX_CLKCMU_DLP_CORE			0x1034
+#define CLK_CON_MUX_CLKCMU_FSYS_BUS			0x1038
+#define CLK_CON_MUX_CLKCMU_FSYS_IP			0x103c
+#define CLK_CON_MUX_CLKCMU_IMEM_ACLK			0x1054
+#define CLK_CON_MUX_CLKCMU_MIF_BUSP			0x1080
+#define CLK_CON_MUX_CLKCMU_MIF_SWITCH			0x1084
+#define CLK_CON_MUX_CLKCMU_PERI_IP			0x1088
+#define CLK_CON_MUX_CLKCMU_RSP_CORE			0x108c
+#define CLK_CON_MUX_CLKCMU_TRFM_CORE			0x1090
+#define CLK_CON_MUX_CLKCMU_VCA_ACE			0x1094
+#define CLK_CON_MUX_CLKCMU_VCA_OD			0x1098
+#define CLK_CON_MUX_CLKCMU_VIO_CORE			0x109c
+#define CLK_CON_MUX_CLKCMU_VIP0_CORE			0x10a0
+#define CLK_CON_MUX_CLKCMU_VIP1_CORE			0x10a4
+#define CLK_CON_MUX_CLKCMU_VPP_CORE			0x10a8
+
+#define CLK_CON_DIV_CLKCMU_BUS				0x1800
+#define CLK_CON_DIV_CLKCMU_BUS_DLP			0x1804
+#define CLK_CON_DIV_CLKCMU_CDC_CORE			0x1808
+#define CLK_CON_DIV_CLKCMU_FSYS_SCAN0			0x180c
+#define CLK_CON_DIV_CLKCMU_FSYS_SCAN1			0x1810
+#define CLK_CON_DIV_CLKCMU_IMEM_JPEG			0x1814
+#define CLK_CON_DIV_CLKCMU_MIF_SWITCH			0x1818
+#define CLK_CON_DIV_CLKCMU_CORE_DLP			0x181c
+#define CLK_CON_DIV_CLKCMU_CORE_MAIN			0x1820
+#define CLK_CON_DIV_CLKCMU_PERI_DISP			0x1824
+#define CLK_CON_DIV_CLKCMU_CPUCL_SWITCH			0x1828
+#define CLK_CON_DIV_CLKCMU_DLP_CORE			0x182c
+#define CLK_CON_DIV_CLKCMU_FSYS_BUS			0x1830
+#define CLK_CON_DIV_CLKCMU_FSYS_IP			0x1834
+#define CLK_CON_DIV_CLKCMU_VIO_AUDIO			0x1838
+#define CLK_CON_DIV_CLKCMU_GPU_2D			0x1848
+#define CLK_CON_DIV_CLKCMU_GPU_3D			0x184c
+#define CLK_CON_DIV_CLKCMU_IMEM_ACLK			0x1854
+#define CLK_CON_DIV_CLKCMU_MIF_BUSP			0x1884
+#define CLK_CON_DIV_CLKCMU_PERI_AUDIO			0x1890
+#define CLK_CON_DIV_CLKCMU_PERI_IP			0x1894
+#define CLK_CON_DIV_CLKCMU_RSP_CORE			0x1898
+#define CLK_CON_DIV_CLKCMU_TRFM_CORE			0x189c
+#define CLK_CON_DIV_CLKCMU_VCA_ACE			0x18a0
+#define CLK_CON_DIV_CLKCMU_VCA_OD			0x18a4
+#define CLK_CON_DIV_CLKCMU_VIO_CORE			0x18ac
+#define CLK_CON_DIV_CLKCMU_VIP0_CORE			0x18b0
+#define CLK_CON_DIV_CLKCMU_VIP1_CORE			0x18b4
+#define CLK_CON_DIV_CLKCMU_VPP_CORE			0x18b8
+#define CLK_CON_DIV_PLL_SHARED0_DIV2			0x18bc
+#define CLK_CON_DIV_PLL_SHARED0_DIV3			0x18c0
+#define CLK_CON_DIV_PLL_SHARED0_DIV4			0x18c4
+#define CLK_CON_DIV_PLL_SHARED1_DIV2			0x18c8
+#define CLK_CON_DIV_PLL_SHARED1_DIV3			0x18cc
+#define CLK_CON_DIV_PLL_SHARED1_DIV4			0x18d0
+
+static const unsigned long cmu_cmu_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_AUDIO,
+	PLL_LOCKTIME_PLL_SHARED0,
+	PLL_LOCKTIME_PLL_SHARED1,
+	PLL_CON0_PLL_AUDIO,
+	PLL_CON0_PLL_SHARED0,
+	PLL_CON0_PLL_SHARED1,
+	CLK_CON_MUX_CLKCMU_2D,
+	CLK_CON_MUX_CLKCMU_3D,
+	CLK_CON_MUX_CLKCMU_BUS,
+	CLK_CON_MUX_CLKCMU_BUS_DLP,
+	CLK_CON_MUX_CLKCMU_CDC_CORE,
+	CLK_CON_MUX_CLKCMU_FSYS_SCAN0,
+	CLK_CON_MUX_CLKCMU_FSYS_SCAN1,
+	CLK_CON_MUX_CLKCMU_IMEM_JPEG,
+	CLK_CON_MUX_CLKCMU_PERI_DISP,
+	CLK_CON_MUX_CLKCMU_CORE_BUS,
+	CLK_CON_MUX_CLKCMU_CORE_DLP,
+	CLK_CON_MUX_CLKCMU_CPUCL_SWITCH,
+	CLK_CON_MUX_CLKCMU_DLP_CORE,
+	CLK_CON_MUX_CLKCMU_FSYS_BUS,
+	CLK_CON_MUX_CLKCMU_FSYS_IP,
+	CLK_CON_MUX_CLKCMU_IMEM_ACLK,
+	CLK_CON_MUX_CLKCMU_MIF_BUSP,
+	CLK_CON_MUX_CLKCMU_MIF_SWITCH,
+	CLK_CON_MUX_CLKCMU_PERI_IP,
+	CLK_CON_MUX_CLKCMU_RSP_CORE,
+	CLK_CON_MUX_CLKCMU_TRFM_CORE,
+	CLK_CON_MUX_CLKCMU_VCA_ACE,
+	CLK_CON_MUX_CLKCMU_VCA_OD,
+	CLK_CON_MUX_CLKCMU_VIO_CORE,
+	CLK_CON_MUX_CLKCMU_VIP0_CORE,
+	CLK_CON_MUX_CLKCMU_VIP1_CORE,
+	CLK_CON_MUX_CLKCMU_VPP_CORE,
+	CLK_CON_DIV_CLKCMU_BUS,
+	CLK_CON_DIV_CLKCMU_BUS_DLP,
+	CLK_CON_DIV_CLKCMU_CDC_CORE,
+	CLK_CON_DIV_CLKCMU_FSYS_SCAN0,
+	CLK_CON_DIV_CLKCMU_FSYS_SCAN1,
+	CLK_CON_DIV_CLKCMU_IMEM_JPEG,
+	CLK_CON_DIV_CLKCMU_MIF_SWITCH,
+	CLK_CON_DIV_CLKCMU_CORE_DLP,
+	CLK_CON_DIV_CLKCMU_CORE_MAIN,
+	CLK_CON_DIV_CLKCMU_PERI_DISP,
+	CLK_CON_DIV_CLKCMU_CPUCL_SWITCH,
+	CLK_CON_DIV_CLKCMU_DLP_CORE,
+	CLK_CON_DIV_CLKCMU_FSYS_BUS,
+	CLK_CON_DIV_CLKCMU_FSYS_IP,
+	CLK_CON_DIV_CLKCMU_VIO_AUDIO,
+	CLK_CON_DIV_CLKCMU_GPU_2D,
+	CLK_CON_DIV_CLKCMU_GPU_3D,
+	CLK_CON_DIV_CLKCMU_IMEM_ACLK,
+	CLK_CON_DIV_CLKCMU_MIF_BUSP,
+	CLK_CON_DIV_CLKCMU_PERI_AUDIO,
+	CLK_CON_DIV_CLKCMU_PERI_IP,
+	CLK_CON_DIV_CLKCMU_RSP_CORE,
+	CLK_CON_DIV_CLKCMU_TRFM_CORE,
+	CLK_CON_DIV_CLKCMU_VCA_ACE,
+	CLK_CON_DIV_CLKCMU_VCA_OD,
+	CLK_CON_DIV_CLKCMU_VIO_CORE,
+	CLK_CON_DIV_CLKCMU_VIP0_CORE,
+	CLK_CON_DIV_CLKCMU_VIP1_CORE,
+	CLK_CON_DIV_CLKCMU_VPP_CORE,
+	CLK_CON_DIV_PLL_SHARED0_DIV2,
+	CLK_CON_DIV_PLL_SHARED0_DIV3,
+	CLK_CON_DIV_PLL_SHARED0_DIV4,
+	CLK_CON_DIV_PLL_SHARED1_DIV2,
+	CLK_CON_DIV_PLL_SHARED1_DIV3,
+	CLK_CON_DIV_PLL_SHARED1_DIV4,
+};
+
+static const struct samsung_pll_rate_table artpec8_pll_audio_rates[] __initconst = {
+	PLL_36XX_RATE(25 * MHZ, 589823913U, 47, 1, 1, 12184),
+	PLL_36XX_RATE(25 * MHZ, 393215942U, 47, 3, 0, 12184),
+	PLL_36XX_RATE(25 * MHZ, 294911956U, 47, 1, 2, 12184),
+	PLL_36XX_RATE(25 * MHZ, 100000000U, 32, 2, 2, 0),
+	PLL_36XX_RATE(25 * MHZ,  98303985U, 47, 3, 2, 12184),
+	PLL_36XX_RATE(25 * MHZ,  49151992U, 47, 3, 3, 12184),
+};
+
+static const struct samsung_pll_clock cmu_cmu_pll_clks[] __initconst = {
+	PLL(pll_1017x, CLK_FOUT_SHARED0_PLL, "fout_pll_shared0", "fin_pll",
+	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL),
+	PLL(pll_1017x, CLK_FOUT_SHARED1_PLL, "fout_pll_shared1", "fin_pll",
+	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, NULL),
+	PLL(pll_1031x, CLK_FOUT_AUDIO_PLL, "fout_pll_audio", "fin_pll",
+	    PLL_LOCKTIME_PLL_AUDIO, PLL_CON0_PLL_AUDIO, artpec8_pll_audio_rates),
+};
+
+PNAME(mout_clkcmu_bus_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_bus_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div4",
+				 "dout_pll_shared1_div2", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_core_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				  "dout_pll_shared0_div4", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_core_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+				  "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_cpucl_switch_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+				      "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_fsys_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2",
+				  "dout_pll_shared1_div4", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_fsys_ip_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
+				 "dout_pll_shared1_div2", "dout_pll_shared0_div3" };
+PNAME(mout_clkcmu_fsys_scan0_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_fsys_scan1_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_imem_imem_p) = { "dout_pll_shared1_div4", "dout_pll_shared0_div3",
+				   "dout_pll_shared1_div3", "dout_pll_shared1_div2" };
+PNAME(mout_clkcmu_imem_jpeg_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div3",
+				   "dout_pll_shared1_div2", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_cdc_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				  "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_dlp_core_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+				  "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_3d_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+			    "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_2d_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
+			    "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_mif_switch_p) = { "dout_pll_shared0", "dout_pll_shared1",
+				    "dout_pll_shared0_div2", "dout_pll_shared0_div3" };
+PNAME(mout_clkcmu_mif_busp_p) = { "dout_pll_shared0_div3", "dout_pll_shared1_div4",
+				  "dout_pll_shared0_div4", "dout_pll_shared0_div2" };
+PNAME(mout_clkcmu_peri_disp_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2",
+				   "dout_pll_shared1_div4", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_peri_ip_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div4",
+				 "dout_pll_shared1_div4", "dout_pll_shared0_div2" };
+PNAME(mout_clkcmu_rsp_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				  "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_trfm_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				   "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vca_ace_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vca_od_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vio_core_p) = { "dout_pll_shared0_div3", "dout_pll_shared0_div2",
+				  "dout_pll_shared1_div2", "dout_pll_shared1_div3" };
+PNAME(mout_clkcmu_vip0_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				   "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vip1_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				   "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_vpp_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
+				  "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
+PNAME(mout_clkcmu_pll_shared0_p) = { "fin_pll", "fout_pll_shared0" };
+PNAME(mout_clkcmu_pll_shared1_p) = { "fin_pll", "fout_pll_shared1" };
+PNAME(mout_clkcmu_pll_audio_p) = { "fin_pll", "fout_pll_audio" };
+
+static const struct samsung_fixed_factor_clock cmu_fixed_factor_clks[] __initconst = {
+	FFACTOR(CLK_DOUT_CMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0),
+};
+
+static const struct samsung_mux_clock cmu_cmu_mux_clks[] __initconst = {
+	MUX(0, "mout_clkcmu_pll_shared0", mout_clkcmu_pll_shared0_p, PLL_CON0_PLL_SHARED0, 4, 1),
+	MUX(0, "mout_clkcmu_pll_shared1", mout_clkcmu_pll_shared1_p, PLL_CON0_PLL_SHARED1, 4, 1),
+	MUX(0, "mout_clkcmu_pll_audio", mout_clkcmu_pll_audio_p, PLL_CON0_PLL_AUDIO, 4, 1),
+	MUX(0, "mout_clkcmu_bus_bus", mout_clkcmu_bus_bus_p, CLK_CON_MUX_CLKCMU_BUS, 0, 2),
+	MUX(0, "mout_clkcmu_bus_dlp", mout_clkcmu_bus_dlp_p, CLK_CON_MUX_CLKCMU_BUS_DLP, 0, 2),
+	MUX(0, "mout_clkcmu_core_bus", mout_clkcmu_core_bus_p, CLK_CON_MUX_CLKCMU_CORE_BUS, 0, 2),
+	MUX(0, "mout_clkcmu_core_dlp", mout_clkcmu_core_dlp_p, CLK_CON_MUX_CLKCMU_CORE_DLP, 0, 2),
+	MUX(0, "mout_clkcmu_cpucl_switch", mout_clkcmu_cpucl_switch_p,
+	    CLK_CON_MUX_CLKCMU_CPUCL_SWITCH, 0, 3),
+	MUX(0, "mout_clkcmu_fsys_bus", mout_clkcmu_fsys_bus_p, CLK_CON_MUX_CLKCMU_FSYS_BUS, 0, 2),
+	MUX(0, "mout_clkcmu_fsys_ip", mout_clkcmu_fsys_ip_p, CLK_CON_MUX_CLKCMU_FSYS_IP, 0, 2),
+	MUX(0, "mout_clkcmu_fsys_scan0", mout_clkcmu_fsys_scan0_p,
+	    CLK_CON_MUX_CLKCMU_FSYS_SCAN0, 0, 1),
+	MUX(0, "mout_clkcmu_fsys_scan1", mout_clkcmu_fsys_scan1_p,
+	    CLK_CON_MUX_CLKCMU_FSYS_SCAN1, 0, 1),
+	MUX(0, "mout_clkcmu_imem_imem", mout_clkcmu_imem_imem_p,
+	    CLK_CON_MUX_CLKCMU_IMEM_ACLK, 0, 2),
+	MUX(0, "mout_clkcmu_imem_jpeg", mout_clkcmu_imem_jpeg_p,
+	    CLK_CON_MUX_CLKCMU_IMEM_JPEG, 0, 2),
+	nMUX(0, "mout_clkcmu_cdc_core", mout_clkcmu_cdc_core_p, CLK_CON_MUX_CLKCMU_CDC_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_dlp_core", mout_clkcmu_dlp_core_p, CLK_CON_MUX_CLKCMU_DLP_CORE, 0, 2),
+	MUX(0, "mout_clkcmu_3d", mout_clkcmu_3d_p, CLK_CON_MUX_CLKCMU_3D, 0, 2),
+	MUX(0, "mout_clkcmu_2d", mout_clkcmu_2d_p, CLK_CON_MUX_CLKCMU_2D, 0, 2),
+	MUX(0, "mout_clkcmu_mif_switch", mout_clkcmu_mif_switch_p,
+	    CLK_CON_MUX_CLKCMU_MIF_SWITCH, 0, 2),
+	MUX(0, "mout_clkcmu_mif_busp", mout_clkcmu_mif_busp_p, CLK_CON_MUX_CLKCMU_MIF_BUSP, 0, 2),
+	MUX(0, "mout_clkcmu_peri_disp", mout_clkcmu_peri_disp_p,
+	    CLK_CON_MUX_CLKCMU_PERI_DISP, 0, 2),
+	MUX(0, "mout_clkcmu_peri_ip", mout_clkcmu_peri_ip_p, CLK_CON_MUX_CLKCMU_PERI_IP, 0, 2),
+	MUX(0, "mout_clkcmu_rsp_core", mout_clkcmu_rsp_core_p, CLK_CON_MUX_CLKCMU_RSP_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_trfm_core", mout_clkcmu_trfm_core_p,
+	     CLK_CON_MUX_CLKCMU_TRFM_CORE, 0, 2),
+	MUX(0, "mout_clkcmu_vca_ace", mout_clkcmu_vca_ace_p, CLK_CON_MUX_CLKCMU_VCA_ACE, 0, 2),
+	MUX(0, "mout_clkcmu_vca_od", mout_clkcmu_vca_od_p, CLK_CON_MUX_CLKCMU_VCA_OD, 0, 2),
+	MUX(0, "mout_clkcmu_vio_core", mout_clkcmu_vio_core_p, CLK_CON_MUX_CLKCMU_VIO_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_vip0_core", mout_clkcmu_vip0_core_p,
+	     CLK_CON_MUX_CLKCMU_VIP0_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_vip1_core", mout_clkcmu_vip1_core_p,
+	     CLK_CON_MUX_CLKCMU_VIP1_CORE, 0, 2),
+	nMUX(0, "mout_clkcmu_vpp_core", mout_clkcmu_vpp_core_p, CLK_CON_MUX_CLKCMU_VPP_CORE, 0, 2),
+};
+
+static const struct samsung_div_clock cmu_cmu_div_clks[] __initconst = {
+	DIV(CLK_DOUT_SHARED0_DIV2, "dout_pll_shared0_div2",
+	    "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+	DIV(CLK_DOUT_SHARED0_DIV3, "dout_pll_shared0_div3",
+	    "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+	DIV(CLK_DOUT_SHARED0_DIV4, "dout_pll_shared0_div4",
+	    "dout_pll_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+	DIV(CLK_DOUT_SHARED1_DIV2, "dout_pll_shared1_div2",
+	    "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+	DIV(CLK_DOUT_SHARED1_DIV3, "dout_pll_shared1_div3",
+	    "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+	DIV(CLK_DOUT_SHARED1_DIV4, "dout_pll_shared1_div4",
+	    "dout_pll_shared1_div2", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+	DIV(CLK_DOUT_CMU_BUS, "dout_clkcmu_bus",
+	    "mout_clkcmu_bus_bus", CLK_CON_DIV_CLKCMU_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_BUS_DLP, "dout_clkcmu_bus_dlp",
+	    "mout_clkcmu_bus_dlp", CLK_CON_DIV_CLKCMU_BUS_DLP, 0, 4),
+	DIV(CLK_DOUT_CMU_CORE_MAIN, "dout_clkcmu_core_main",
+	    "mout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_MAIN, 0, 4),
+	DIV(CLK_DOUT_CMU_CORE_DLP, "dout_clkcmu_core_dlp",
+	    "mout_clkcmu_core_dlp", CLK_CON_DIV_CLKCMU_CORE_DLP, 0, 4),
+	DIV(CLK_DOUT_CMU_CPUCL_SWITCH, "dout_clkcmu_cpucl_switch",
+	    "mout_clkcmu_cpucl_switch", CLK_CON_DIV_CLKCMU_CPUCL_SWITCH, 0, 3),
+	DIV(CLK_DOUT_CMU_FSYS_BUS, "dout_clkcmu_fsys_bus",
+	    "mout_clkcmu_fsys_bus", CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_FSYS_IP, "dout_clkcmu_fsys_ip",
+	    "mout_clkcmu_fsys_ip", CLK_CON_DIV_CLKCMU_FSYS_IP, 0, 9),
+	DIV(CLK_DOUT_CMU_FSYS_SCAN0, "dout_clkcmu_fsys_scan0",
+	    "mout_clkcmu_fsys_scan0", CLK_CON_DIV_CLKCMU_FSYS_SCAN0, 0, 4),
+	DIV(CLK_DOUT_CMU_FSYS_SCAN1, "dout_clkcmu_fsys_scan1",
+	    "mout_clkcmu_fsys_scan1", CLK_CON_DIV_CLKCMU_FSYS_SCAN1, 0, 4),
+	DIV(CLK_DOUT_CMU_IMEM_ACLK, "dout_clkcmu_imem_aclk",
+	    "mout_clkcmu_imem_imem", CLK_CON_DIV_CLKCMU_IMEM_ACLK, 0, 4),
+	DIV(CLK_DOUT_CMU_IMEM_JPEG, "dout_clkcmu_imem_jpeg",
+	    "mout_clkcmu_imem_jpeg", CLK_CON_DIV_CLKCMU_IMEM_JPEG, 0, 4),
+	DIV_F(CLK_DOUT_CMU_CDC_CORE, "dout_clkcmu_cdc_core",
+	      "mout_clkcmu_cdc_core", CLK_CON_DIV_CLKCMU_CDC_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
+	DIV_F(CLK_DOUT_CMU_DLP_CORE, "dout_clkcmu_dlp_core",
+	      "mout_clkcmu_dlp_core", CLK_CON_DIV_CLKCMU_DLP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DOUT_CMU_GPU_3D, "dout_clkcmu_gpu_3d",
+	    "mout_clkcmu_3d", CLK_CON_DIV_CLKCMU_GPU_3D, 0, 3),
+	DIV(CLK_DOUT_CMU_GPU_2D, "dout_clkcmu_gpu_2d",
+	    "mout_clkcmu_2d", CLK_CON_DIV_CLKCMU_GPU_2D, 0, 4),
+	DIV(CLK_DOUT_CMU_MIF_SWITCH, "dout_clkcmu_mif_switch",
+	    "mout_clkcmu_mif_switch", CLK_CON_DIV_CLKCMU_MIF_SWITCH, 0, 4),
+	DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_clkcmu_mif_busp",
+	    "mout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 3),
+	DIV(CLK_DOUT_CMU_PERI_DISP, "dout_clkcmu_peri_disp",
+	    "mout_clkcmu_peri_disp", CLK_CON_DIV_CLKCMU_PERI_DISP, 0, 4),
+	DIV(CLK_DOUT_CMU_PERI_IP, "dout_clkcmu_peri_ip",
+	    "mout_clkcmu_peri_ip", CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
+	DIV(CLK_DOUT_CMU_PERI_AUDIO, "dout_clkcmu_peri_audio",
+	    "mout_clkcmu_pll_audio", CLK_CON_DIV_CLKCMU_PERI_AUDIO, 0, 4),
+	DIV(CLK_DOUT_CMU_RSP_CORE, "dout_clkcmu_rsp_core",
+	    "mout_clkcmu_rsp_core", CLK_CON_DIV_CLKCMU_RSP_CORE, 0, 4),
+	DIV_F(CLK_DOUT_CMU_TRFM_CORE, "dout_clkcmu_trfm_core",
+	      "mout_clkcmu_trfm_core", CLK_CON_DIV_CLKCMU_TRFM_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DOUT_CMU_VCA_ACE, "dout_clkcmu_vca_ace",
+	    "mout_clkcmu_vca_ace", CLK_CON_DIV_CLKCMU_VCA_ACE, 0, 4),
+	DIV(CLK_DOUT_CMU_VCA_OD, "dout_clkcmu_vca_od",
+	    "mout_clkcmu_vca_od", CLK_CON_DIV_CLKCMU_VCA_OD, 0, 4),
+	DIV(CLK_DOUT_CMU_VIO_CORE, "dout_clkcmu_vio_core",
+	    "mout_clkcmu_vio_core", CLK_CON_DIV_CLKCMU_VIO_CORE, 0, 4),
+	DIV(CLK_DOUT_CMU_VIO_AUDIO, "dout_clkcmu_vio_audio",
+	    "mout_clkcmu_pll_audio", CLK_CON_DIV_CLKCMU_VIO_AUDIO, 0, 4),
+	DIV_F(CLK_DOUT_CMU_VIP0_CORE, "dout_clkcmu_vip0_core",
+	      "mout_clkcmu_vip0_core", CLK_CON_DIV_CLKCMU_VIP0_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
+	DIV_F(CLK_DOUT_CMU_VIP1_CORE, "dout_clkcmu_vip1_core",
+	      "mout_clkcmu_vip1_core", CLK_CON_DIV_CLKCMU_VIP1_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
+	DIV_F(CLK_DOUT_CMU_VPP_CORE, "dout_clkcmu_vpp_core",
+	      "mout_clkcmu_vpp_core", CLK_CON_DIV_CLKCMU_VPP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_cmu_info cmu_cmu_info __initconst = {
+	.pll_clks		= cmu_cmu_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(cmu_cmu_pll_clks),
+	.fixed_factor_clks	= cmu_fixed_factor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(cmu_fixed_factor_clks),
+	.mux_clks		= cmu_cmu_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_cmu_mux_clks),
+	.div_clks		= cmu_cmu_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_cmu_div_clks),
+	.nr_clk_ids		= CMU_CMU_NR_CLK,
+	.clk_regs		= cmu_cmu_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_cmu_clk_regs),
+};
+
+/* Register Offset definitions for CMU_BUS (0x12c10000) */
+#define PLL_CON0_MUX_CLK_BUS_ACLK_USER			0x0100
+#define PLL_CON0_MUX_CLK_BUS_DLP_USER			0x0120
+#define CLK_CON_DIV_CLK_BUS_PCLK			0x1800
+
+static const unsigned long cmu_bus_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLK_BUS_ACLK_USER,
+	PLL_CON0_MUX_CLK_BUS_DLP_USER,
+	CLK_CON_DIV_CLK_BUS_PCLK,
+};
+
+PNAME(mout_clk_bus_aclk_user_p) = { "fin_pll", "dout_clkcmu_bus" };
+PNAME(mout_clk_bus_dlp_user_p) = { "fin_pll", "dout_clkcmu_bus_dlp" };
+
+static const struct samsung_mux_clock cmu_bus_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_BUS_ACLK_USER, "mout_clk_bus_aclk_user",
+	    mout_clk_bus_aclk_user_p, PLL_CON0_MUX_CLK_BUS_ACLK_USER, 4, 1),
+	MUX(CLK_MOUT_BUS_DLP_USER, "mout_clk_bus_dlp_user",
+	    mout_clk_bus_dlp_user_p, PLL_CON0_MUX_CLK_BUS_DLP_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_bus_div_clks[] __initconst = {
+	DIV(CLK_DOUT_BUS_PCLK, "dout_clk_bus_pclk", "mout_clk_bus_aclk_user",
+	    CLK_CON_DIV_CLK_BUS_PCLK, 0, 4),
+};
+
+static const struct samsung_cmu_info cmu_bus_info __initconst = {
+	.mux_clks		= cmu_bus_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_bus_mux_clks),
+	.div_clks		= cmu_bus_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_bus_div_clks),
+	.nr_clk_ids		= CMU_BUS_NR_CLK,
+	.clk_regs		= cmu_bus_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_bus_clk_regs),
+};
+
+/* Register Offset definitions for CMU_CORE (0x12410000) */
+#define PLL_CON0_MUX_CLK_CORE_ACLK_USER			0x0100
+#define PLL_CON0_MUX_CLK_CORE_DLP_USER			0x0120
+#define CLK_CON_DIV_CLK_CORE_PCLK			0x1800
+
+static const unsigned long cmu_core_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLK_CORE_ACLK_USER,
+	PLL_CON0_MUX_CLK_CORE_DLP_USER,
+	CLK_CON_DIV_CLK_CORE_PCLK,
+};
+
+PNAME(mout_clk_core_aclk_user_p) = { "fin_pll", "dout_clkcmu_core_main" };
+PNAME(mout_clk_core_dlp_user_p) = { "fin_pll", "dout_clkcmu_core_dlp" };
+
+static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_CORE_ACLK_USER, "mout_clk_core_aclk_user",
+	    mout_clk_core_aclk_user_p, PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1),
+	MUX(CLK_MOUT_CORE_DLP_USER, "mout_clk_core_dlp_user",
+	    mout_clk_core_dlp_user_p, PLL_CON0_MUX_CLK_CORE_DLP_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_core_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CORE_PCLK, "dout_clk_core_pclk",
+	    "mout_clk_core_aclk_user", CLK_CON_DIV_CLK_CORE_PCLK, 0, 4),
+};
+
+static const struct samsung_cmu_info cmu_core_info __initconst = {
+	.mux_clks		= cmu_core_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_core_mux_clks),
+	.div_clks		= cmu_core_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_core_div_clks),
+	.nr_clk_ids		= CMU_CORE_NR_CLK,
+	.clk_regs		= cmu_core_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_core_clk_regs),
+};
+
+/* Register Offset definitions for CMU_CPUCL (0x11410000) */
+#define PLL_LOCKTIME_PLL_CPUCL				0x0000
+#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER		0x0120
+#define PLL_CON0_PLL_CPUCL				0x0140
+#define CLK_CON_MUX_CLK_CPUCL_PLL			0x1000
+#define CLK_CON_DIV_CLK_CLUSTER_ACLK			0x1800
+#define CLK_CON_DIV_CLK_CLUSTER_CNTCLK			0x1804
+#define CLK_CON_DIV_CLK_CLUSTER_PCLKDBG			0x1808
+#define CLK_CON_DIV_CLK_CPUCL_CMUREF			0x180c
+#define CLK_CON_DIV_CLK_CPUCL_PCLK			0x1814
+#define CLK_CON_DIV_CLK_CLUSTER_ATCLK			0x1818
+#define CLK_CON_DIV_CLK_CPUCL_DBG			0x181c
+#define CLK_CON_DIV_CLK_CPUCL_PCLKDBG			0x1820
+#define CLK_CON_GAT_CLK_CLUSTER_CPU			0x2008
+#define CLK_CON_GAT_CLK_CPUCL_SHORTSTOP			0x200c
+#define CLK_CON_DMYQCH_CON_CSSYS_QCH			0x3008
+
+static const unsigned long cmu_cpucl_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_CPUCL,
+	PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER,
+	PLL_CON0_PLL_CPUCL,
+	CLK_CON_MUX_CLK_CPUCL_PLL,
+	CLK_CON_DIV_CLK_CLUSTER_ACLK,
+	CLK_CON_DIV_CLK_CLUSTER_CNTCLK,
+	CLK_CON_DIV_CLK_CLUSTER_PCLKDBG,
+	CLK_CON_DIV_CLK_CPUCL_CMUREF,
+	CLK_CON_DIV_CLK_CPUCL_PCLK,
+	CLK_CON_DIV_CLK_CLUSTER_ATCLK,
+	CLK_CON_DIV_CLK_CPUCL_DBG,
+	CLK_CON_DIV_CLK_CPUCL_PCLKDBG,
+	CLK_CON_GAT_CLK_CLUSTER_CPU,
+	CLK_CON_GAT_CLK_CPUCL_SHORTSTOP,
+	CLK_CON_DMYQCH_CON_CSSYS_QCH,
+};
+
+static const struct samsung_pll_clock cmu_cpucl_pll_clks[] __initconst = {
+	PLL(pll_1017x, CLK_FOUT_CPUCL_PLL, "fout_pll_cpucl", "fin_pll",
+	    PLL_LOCKTIME_PLL_CPUCL, PLL_CON0_PLL_CPUCL, NULL),
+};
+
+PNAME(mout_clkcmu_cpucl_switch_user_p) = { "fin_pll", "dout_clkcmu_cpucl_switch" };
+PNAME(mout_pll_cpucl_p) = { "fin_pll", "fout_pll_cpucl" };
+PNAME(mout_clk_cpucl_pll_p) = { "mout_pll_cpucl", "mout_clkcmu_cpucl_switch_user" };
+
+static const struct samsung_mux_clock cmu_cpucl_mux_clks[] __initconst = {
+	MUX_F(0, "mout_pll_cpucl", mout_pll_cpucl_p, PLL_CON0_PLL_CPUCL, 4, 1,
+	      CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
+	MUX(CLK_MOUT_CPUCL_SWITCH_USER, "mout_clkcmu_cpucl_switch_user",
+	    mout_clkcmu_cpucl_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, 4, 1),
+	MUX_F(CLK_MOUT_CPUCL_PLL, "mout_clk_cpucl_pll", mout_clk_cpucl_pll_p,
+	      CLK_CON_MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_fixed_factor_clock cpucl_ffactor_clks[] __initconst = {
+	FFACTOR(CLK_DOUT_CPUCL_CPU, "dout_clk_cpucl_cpu",
+		"mout_clk_cpucl_pll", 1, 1, CLK_SET_RATE_PARENT),
+};
+
+static const struct samsung_div_clock cmu_cpucl_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CPUCL_CLUSTER_ACLK, "dout_clk_cluster_aclk",
+	    "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_ACLK, 0, 4),
+	DIV(CLK_DOUT_CPUCL_CLUSTER_PCLKDBG, "dout_clk_cluster_pclkdbg",
+	    "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_PCLKDBG, 0, 4),
+	DIV(CLK_DOUT_CPUCL_CLUSTER_CNTCLK, "dout_clk_cluster_cntclk",
+	    "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_CNTCLK, 0, 4),
+	DIV(CLK_DOUT_CPUCL_CLUSTER_ATCLK, "dout_clk_cluster_atclk",
+	    "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_ATCLK, 0, 4),
+	DIV(CLK_DOUT_CPUCL_PCLK, "dout_clk_cpucl_pclk",
+	    "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_PCLK, 0, 4),
+	DIV(CLK_DOUT_CPUCL_CMUREF, "dout_clk_cpucl_cmuref",
+	    "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_CMUREF, 0, 3),
+	DIV(CLK_DOUT_CPUCL_DBG, "dout_clk_cpucl_dbg",
+	    "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_DBG, 0, 4),
+	DIV(CLK_DOUT_CPUCL_PCLKDBG, "dout_clk_cpucl_pclkdbg",
+	    "dout_clk_cpucl_dbg", CLK_CON_DIV_CLK_CPUCL_PCLKDBG, 0, 4),
+};
+
+static const struct samsung_gate_clock cmu_cpucl_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CPUCL_CLUSTER_CPU, "clk_con_gat_clk_cluster_cpu",
+	     "clk_con_gat_clk_cpucl_shortstop", CLK_CON_GAT_CLK_CLUSTER_CPU, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_CPUCL_SHORTSTOP, "clk_con_gat_clk_cpucl_shortstop",
+	     "dout_clk_cpucl_cpu", CLK_CON_GAT_CLK_CPUCL_SHORTSTOP, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG, "cssys_ipclkport_pclkdbg",
+	     "dout_clk_cpucl_pclkdbg", CLK_CON_DMYQCH_CON_CSSYS_QCH, 1,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK, "cssys_ipclkport_atclk",
+	     "dout_clk_cpucl_dbg", CLK_CON_DMYQCH_CON_CSSYS_QCH, 1,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_cpucl_info __initconst = {
+	.pll_clks		= cmu_cpucl_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(cmu_cpucl_pll_clks),
+	.fixed_factor_clks	= cpucl_ffactor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(cpucl_ffactor_clks),
+	.mux_clks		= cmu_cpucl_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_cpucl_mux_clks),
+	.div_clks		= cmu_cpucl_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_cpucl_div_clks),
+	.gate_clks              = cmu_cpucl_gate_clks,
+	.nr_gate_clks           = ARRAY_SIZE(cmu_cpucl_gate_clks),
+	.nr_clk_ids		= CMU_CPUCL_NR_CLK,
+	.clk_regs		= cmu_cpucl_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_cpucl_clk_regs),
+};
+
+/* Register Offset definitions for CMU_FSYS (0x16c10000) */
+#define PLL_LOCKTIME_PLL_FSYS				0x0004
+#define PLL_CON0_MUX_CLK_FSYS_BUS_USER			0x0120
+#define PLL_CON0_MUX_CLK_FSYS_MMC_USER			0x0140
+#define PLL_CON0_MUX_CLK_FSYS_SCAN0_USER		0x0160
+#define PLL_CON0_MUX_CLK_FSYS_SCAN1_USER		0x0180
+#define PLL_CON0_PLL_FSYS				0x01c0
+#define CLK_CON_DIV_CLK_FSYS_ADC			0x1804
+#define CLK_CON_DIV_CLK_FSYS_BUS300			0x1808
+#define CLK_CON_DIV_CLK_FSYS_BUS_QSPI			0x180c
+#define CLK_CON_DIV_CLK_FSYS_EQOS_25			0x1810
+#define CLK_CON_DIV_CLK_FSYS_EQOS_2P5			0x1814
+#define CLK_CON_DIV_CLK_FSYS_EQOS_500			0x1818
+#define CLK_CON_DIV_CLK_FSYS_EQOS_INT125		0x181c
+#define CLK_CON_DIV_CLK_FSYS_MMC_CARD0			0x1820
+#define CLK_CON_DIV_CLK_FSYS_MMC_CARD1			0x1824
+#define CLK_CON_DIV_CLK_FSYS_OTP_MEM			0x1828
+#define CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL	0x182c
+#define CLK_CON_DIV_CLK_FSYS_QSPI			0x1830
+#define CLK_CON_DIV_CLK_FSYS_SCLK_UART			0x1834
+#define CLK_CON_DIV_CLK_FSYS_SFMC_NAND			0x1838
+#define CLK_CON_DIV_SCAN_CLK_FSYS_125			0x183c
+#define CLK_CON_DIV_SCAN_CLK_FSYS_MMC			0x1840
+#define CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE		0x1844
+#define CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK		0x2044
+#define CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK		0x2048
+#define CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK		0x204c
+#define CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART	0x2050
+#define CLK_CON_MMC0_IPCLKPORT_I_ACLK			0x2070
+#define CLK_CON_MMC1_IPCLKPORT_I_ACLK			0x2078
+#define CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG		0x208c
+#define CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG	0x2090
+#define CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG		0x2094
+#define CLK_CON_PWM_IPCLKPORT_I_PCLK_S0			0x20a0
+#define CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20	0x20bc
+#define CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY	0x20c0
+#define CLK_CON_XHB_AHBBR_IPCLKPORT_CLK			0x20c4
+#define CLK_CON_XHB_USB_IPCLKPORT_CLK			0x20cc
+#define CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK		0x201c
+#define CLK_CON_DMYQCH_CON_EQOS_TOP_QCH			0x3008
+#define CLK_CON_DMYQCH_CON_MMC0_QCH			0x300c
+#define CLK_CON_DMYQCH_CON_MMC1_QCH			0x3010
+#define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH			0x3018
+#define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF		0x301c
+#define CLK_CON_DMYQCH_CON_QSPI_QCH			0x3020
+#define CLK_CON_DMYQCH_CON_SFMC_QCH			0x3024
+
+static const unsigned long cmu_fsys_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_FSYS,
+	PLL_CON0_MUX_CLK_FSYS_BUS_USER,
+	PLL_CON0_MUX_CLK_FSYS_MMC_USER,
+	PLL_CON0_MUX_CLK_FSYS_SCAN0_USER,
+	PLL_CON0_MUX_CLK_FSYS_SCAN1_USER,
+	PLL_CON0_PLL_FSYS,
+	CLK_CON_DIV_CLK_FSYS_ADC,
+	CLK_CON_DIV_CLK_FSYS_BUS300,
+	CLK_CON_DIV_CLK_FSYS_BUS_QSPI,
+	CLK_CON_DIV_CLK_FSYS_EQOS_25,
+	CLK_CON_DIV_CLK_FSYS_EQOS_2P5,
+	CLK_CON_DIV_CLK_FSYS_EQOS_500,
+	CLK_CON_DIV_CLK_FSYS_EQOS_INT125,
+	CLK_CON_DIV_CLK_FSYS_MMC_CARD0,
+	CLK_CON_DIV_CLK_FSYS_MMC_CARD1,
+	CLK_CON_DIV_CLK_FSYS_OTP_MEM,
+	CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL,
+	CLK_CON_DIV_CLK_FSYS_QSPI,
+	CLK_CON_DIV_CLK_FSYS_SCLK_UART,
+	CLK_CON_DIV_CLK_FSYS_SFMC_NAND,
+	CLK_CON_DIV_SCAN_CLK_FSYS_125,
+	CLK_CON_DIV_SCAN_CLK_FSYS_MMC,
+	CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE,
+	CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK,
+	CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK,
+	CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK,
+	CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART,
+	CLK_CON_MMC0_IPCLKPORT_I_ACLK,
+	CLK_CON_MMC1_IPCLKPORT_I_ACLK,
+	CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+	CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+	CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+	CLK_CON_PWM_IPCLKPORT_I_PCLK_S0,
+	CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
+	CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY,
+	CLK_CON_XHB_AHBBR_IPCLKPORT_CLK,
+	CLK_CON_XHB_USB_IPCLKPORT_CLK,
+	CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK,
+	CLK_CON_DMYQCH_CON_EQOS_TOP_QCH,
+	CLK_CON_DMYQCH_CON_MMC0_QCH,
+	CLK_CON_DMYQCH_CON_MMC1_QCH,
+	CLK_CON_DMYQCH_CON_PCIE_TOP_QCH,
+	CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF,
+	CLK_CON_DMYQCH_CON_QSPI_QCH,
+	CLK_CON_DMYQCH_CON_SFMC_QCH,
+};
+
+static const struct samsung_pll_clock cmu_fsys_pll_clks[] __initconst = {
+	PLL(pll_1017x, CLK_FOUT_FSYS_PLL, "fout_pll_fsys", "fin_pll",
+	    PLL_LOCKTIME_PLL_FSYS, PLL_CON0_PLL_FSYS, NULL),
+};
+
+PNAME(mout_fsys_scan0_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan0" };
+PNAME(mout_fsys_scan1_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan1" };
+PNAME(mout_fsys_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys_bus" };
+PNAME(mout_fsys_mmc_user_p) = { "fin_pll", "dout_clkcmu_fsys_ip" };
+PNAME(mout_fsys_pll_fsys_p) = { "fin_pll", "fout_pll_fsys" };
+
+static const struct samsung_mux_clock cmu_fsys_mux_clks[] __initconst = {
+	MUX(0, "mout_clk_pll_fsys", mout_fsys_pll_fsys_p, PLL_CON0_PLL_FSYS, 4, 1),
+	MUX(CLK_MOUT_FSYS_SCAN0_USER, "mout_fsys_scan0_user",
+	    mout_fsys_scan0_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN0_USER, 4, 1),
+	MUX(CLK_MOUT_FSYS_SCAN1_USER, "mout_fsys_scan1_user",
+	    mout_fsys_scan1_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN1_USER, 4, 1),
+	MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user",
+	    mout_fsys_bus_user_p, PLL_CON0_MUX_CLK_FSYS_BUS_USER, 4, 1),
+	MUX(CLK_MOUT_FSYS_MMC_USER, "mout_fsys_mmc_user",
+	    mout_fsys_mmc_user_p, PLL_CON0_MUX_CLK_FSYS_MMC_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cmu_fsys_div_clks[] __initconst = {
+	DIV(CLK_DOUT_FSYS_PCIE_PIPE, "dout_fsys_pcie_pipe", "mout_clk_pll_fsys",
+	    CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE, 0, 4),
+	DIV(CLK_DOUT_FSYS_ADC, "dout_fsys_adc", "mout_clk_pll_fsys",
+	    CLK_CON_DIV_CLK_FSYS_ADC, 0, 7),
+	DIV(CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL, "dout_fsys_pcie_phy_refclk_syspll",
+	    "mout_clk_pll_fsys", CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, 0, 8),
+	DIV(CLK_DOUT_FSYS_QSPI, "dout_fsys_qspi", "mout_fsys_mmc_user",
+	    CLK_CON_DIV_CLK_FSYS_QSPI, 0, 4),
+	DIV(CLK_DOUT_FSYS_EQOS_INT125, "dout_fsys_eqos_int125", "mout_clk_pll_fsys",
+	    CLK_CON_DIV_CLK_FSYS_EQOS_INT125, 0, 4),
+	DIV(CLK_DOUT_FSYS_OTP_MEM, "dout_fsys_otp_mem", "fin_pll",
+	    CLK_CON_DIV_CLK_FSYS_OTP_MEM, 0, 9),
+	DIV(CLK_DOUT_FSYS_SCLK_UART, "dout_fsys_sclk_uart", "mout_clk_pll_fsys",
+	    CLK_CON_DIV_CLK_FSYS_SCLK_UART, 0, 10),
+	DIV(CLK_DOUT_FSYS_SFMC_NAND, "dout_fsys_sfmc_nand", "mout_fsys_mmc_user",
+	    CLK_CON_DIV_CLK_FSYS_SFMC_NAND, 0, 4),
+	DIV(CLK_DOUT_SCAN_CLK_FSYS_125, "dout_scan_clk_fsys_125", "mout_clk_pll_fsys",
+	    CLK_CON_DIV_SCAN_CLK_FSYS_125, 0, 4),
+	DIV(CLK_DOUT_FSYS_SCAN_CLK_MMC, "dout_scan_clk_fsys_mmc", "fout_pll_fsys",
+	    CLK_CON_DIV_SCAN_CLK_FSYS_MMC, 0, 4),
+	DIV(CLK_DOUT_FSYS_EQOS_25, "dout_fsys_eqos_25", "dout_fsys_eqos_int125",
+	    CLK_CON_DIV_CLK_FSYS_EQOS_25, 0, 4),
+	DIV_F(CLK_DOUT_FSYS_EQOS_2p5, "dout_fsys_eqos_2p5", "dout_fsys_eqos_25",
+	      CLK_CON_DIV_CLK_FSYS_EQOS_2P5, 0, 4, CLK_SET_RATE_PARENT, 0),
+	DIV(0, "dout_fsys_eqos_500", "mout_clk_pll_fsys",
+	    CLK_CON_DIV_CLK_FSYS_EQOS_500, 0, 4),
+	DIV(CLK_DOUT_FSYS_BUS300, "dout_fsys_bus300", "mout_fsys_bus_user",
+	    CLK_CON_DIV_CLK_FSYS_BUS300, 0, 4),
+	DIV(CLK_DOUT_FSYS_BUS_QSPI, "dout_fsys_bus_qspi", "mout_fsys_mmc_user",
+	    CLK_CON_DIV_CLK_FSYS_BUS_QSPI, 0, 4),
+	DIV(CLK_DOUT_FSYS_MMC_CARD0, "dout_fsys_mmc_card0", "mout_fsys_mmc_user",
+	    CLK_CON_DIV_CLK_FSYS_MMC_CARD0, 0, 10),
+	DIV(CLK_DOUT_FSYS_MMC_CARD1, "dout_fsys_mmc_card1", "mout_fsys_mmc_user",
+	    CLK_CON_DIV_CLK_FSYS_MMC_CARD1, 0, 10),
+};
+
+static const struct samsung_gate_clock cmu_fsys_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN, "pcie_sub_ctrl_inst_0_phy_refclk_in",
+	     "dout_fsys_pcie_phy_refclk_syspll", CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF, 1,
+	     CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5,
+	     "eqos_top_ipclkport_i_rgmii_txclk_2p5",
+	     "dout_fsys_eqos_2p5", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I, "eqos_top_ipclkport_aclk_i",
+	     "dout_fsys_bus300", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I, "eqos_top_ipclkport_clk_csr_i",
+	     "dout_fsys_bus300", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK, "pipe_pal_inst_0_i_apb_pclk",
+	     "dout_fsys_bus300", CLK_CON_DMYQCH_CON_PCIE_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK, "qspi_ipclkport_hclk",
+	     "dout_fsys_bus_qspi", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK, "qspi_ipclkport_ssi_clk",
+	     "dout_fsys_qspi", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN, "mmc0_ipclkport_sdclkin",
+	     "dout_fsys_mmc_card0", CLK_CON_DMYQCH_CON_MMC0_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN, "mmc1_ipclkport_sdclkin",
+	     "dout_fsys_mmc_card1", CLK_CON_DMYQCH_CON_MMC1_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND, "sfmc_ipclkport_i_aclk_nand",
+	     "dout_fsys_sfmc_nand", CLK_CON_DMYQCH_CON_SFMC_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_FSYS_UART0_SCLK_UART, "uart0_sclk", "dout_fsys_sclk_uart",
+	     CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, "dwc_pcie_ctl_inst_0_mstr_aclk_ug",
+	     "mout_fsys_bus_user", CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG, "dwc_pcie_ctl_inst_0_slv_aclk_ug",
+	     "mout_fsys_bus_user", CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK, "fsys_i2c0_ipclkport_i_pclk", "dout_fsys_bus300",
+	     CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK, "fsys_i2c1_ipclkport_i_pclk", "dout_fsys_bus300",
+	     CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_UART0_PCLK, "uart0_pclk", "dout_fsys_bus300",
+	     CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK, "mmc0_ipclkport_i_aclk", "dout_fsys_bus300",
+	     CLK_CON_MMC0_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK, "mmc1_ipclkport_i_aclk", "dout_fsys_bus300",
+	     CLK_CON_MMC1_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, "dwc_pcie_ctl_inst_0_dbi_aclk_ug",
+	     "dout_fsys_bus300", CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0, "pwm_ipclkport_i_pclk_s0", "dout_fsys_bus300",
+	     CLK_CON_PWM_IPCLKPORT_I_PCLK_S0, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, "usb20drd_ipclkport_aclk_phyctrl_20",
+	     "dout_fsys_bus300", CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, "usb20drd_ipclkport_bus_clk_early",
+	     "dout_fsys_bus300", CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK, "xhb_ahbbr_ipclkport_clk", "dout_fsys_bus300",
+	     CLK_CON_XHB_AHBBR_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK, "xhb_usb_ipclkport_clk", "dout_fsys_bus300",
+	     CLK_CON_XHB_USB_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_FSYS_BUS_QSPI, "bus_p_fsys_ipclkport_qspiclk", "dout_fsys_bus_qspi",
+	     CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_fsys_info __initconst = {
+	.pll_clks		= cmu_fsys_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(cmu_fsys_pll_clks),
+	.mux_clks		= cmu_fsys_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_fsys_mux_clks),
+	.div_clks		= cmu_fsys_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_fsys_div_clks),
+	.gate_clks              = cmu_fsys_gate_clks,
+	.nr_gate_clks           = ARRAY_SIZE(cmu_fsys_gate_clks),
+	.nr_clk_ids		= CMU_FSYS_NR_CLK,
+	.clk_regs		= cmu_fsys_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_fsys_clk_regs),
+};
+
+/* Register Offset definitions for CMU_IMEM (0x10010000) */
+#define PLL_CON0_MUX_CLK_IMEM_ACLK_USER			0x0100
+#define PLL_CON0_MUX_CLK_IMEM_JPEG_USER			0x0120
+#define CLK_CON_MUX_CLK_IMEM_GIC_CA53			0x1000
+#define CLK_CON_MUX_CLK_IMEM_GIC_CA5			0x1008
+#define CLK_CON_MCT_IPCLKPORT_PCLK			0x2038
+#define CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK		0x2044
+
+static const unsigned long cmu_imem_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLK_IMEM_ACLK_USER,
+	PLL_CON0_MUX_CLK_IMEM_JPEG_USER,
+	CLK_CON_MUX_CLK_IMEM_GIC_CA53,
+	CLK_CON_MUX_CLK_IMEM_GIC_CA5,
+	CLK_CON_MCT_IPCLKPORT_PCLK,
+	CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK,
+};
+
+PNAME(mout_imem_aclk_user_p) = { "fin_pll", "dout_clkcmu_imem_aclk" };
+PNAME(mout_imem_gic_ca53_p) = { "mout_imem_aclk_user", "fin_pll" };
+PNAME(mout_imem_gic_ca5_p) = { "mout_imem_aclk_user", "fin_pll" };
+PNAME(mout_imem_jpeg_user_p) = { "fin_pll", "dout_clkcmu_imem_jpeg" };
+
+static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_IMEM_ACLK_USER, "mout_imem_aclk_user",
+	    mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1),
+	MUX(CLK_MOUT_IMEM_GIC_CA53, "mout_imem_gic_ca53",
+	    mout_imem_gic_ca53_p, CLK_CON_MUX_CLK_IMEM_GIC_CA53, 0, 1),
+	MUX(CLK_MOUT_IMEM_GIC_CA5, "mout_imem_gic_ca5",
+	    mout_imem_gic_ca5_p, CLK_CON_MUX_CLK_IMEM_GIC_CA5, 0, 1),
+	MUX(CLK_MOUT_IMEM_JPEG_USER, "mout_imem_jpeg_user",
+	    mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1),
+};
+
+static const struct samsung_gate_clock cmu_imem_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_IMEM_MCT_PCLK, "mct_pclk", "mout_imem_aclk_user",
+	     CLK_CON_MCT_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_IMEM_PCLK_TMU0_APBIF, "sfrif_tmu_imem_ipclkport_pclk", "mout_imem_aclk_user",
+	     CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_imem_info __initconst = {
+	.mux_clks		= cmu_imem_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_imem_mux_clks),
+	.gate_clks              = cmu_imem_gate_clks,
+	.nr_gate_clks           = ARRAY_SIZE(cmu_imem_gate_clks),
+	.nr_clk_ids		= CMU_IMEM_NR_CLK,
+	.clk_regs		= cmu_imem_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_imem_clk_regs),
+};
+
+static void __init artpec8_clk_cmu_imem_init(struct device_node *np)
+{
+	samsung_cmu_register_one(np, &cmu_imem_info);
+}
+
+CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init);
+
+/* Register Offset definitions for CMU_PERI (0x16410000) */
+#define PLL_CON0_MUX_CLK_PERI_AUDIO_USER		0x0100
+#define PLL_CON0_MUX_CLK_PERI_DISP_USER			0x0120
+#define PLL_CON0_MUX_CLK_PERI_IP_USER			0x0140
+#define CLK_CON_MUX_CLK_PERI_I2S0			0x1000
+#define CLK_CON_MUX_CLK_PERI_I2S1			0x1004
+#define CLK_CON_DIV_CLK_PERI_DSIM			0x1800
+#define CLK_CON_DIV_CLK_PERI_I2S0			0x1804
+#define CLK_CON_DIV_CLK_PERI_I2S1			0x1808
+#define CLK_CON_DIV_CLK_PERI_PCLK			0x180c
+#define CLK_CON_DIV_CLK_PERI_SPI			0x1810
+#define CLK_CON_DIV_CLK_PERI_UART1			0x1814
+#define CLK_CON_DIV_CLK_PERI_UART2			0x1818
+#define CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS		0x2004
+#define CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK		0x2030
+#define CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK		0x2034
+#define CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK		0x2048
+#define CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI		0x204c
+#define CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK		0x2050
+#define CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART	0x2054
+#define CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK		0x2058
+#define CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART	0x205c
+#define CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH		0x3000
+#define CLK_CON_DMYQCH_CON_DMA4DSIM_QCH			0x3004
+#define CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH		0x3008
+#define CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH		0x300c
+
+static const unsigned long cmu_peri_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLK_PERI_AUDIO_USER,
+	PLL_CON0_MUX_CLK_PERI_DISP_USER,
+	PLL_CON0_MUX_CLK_PERI_IP_USER,
+	CLK_CON_MUX_CLK_PERI_I2S0,
+	CLK_CON_MUX_CLK_PERI_I2S1,
+	CLK_CON_DIV_CLK_PERI_DSIM,
+	CLK_CON_DIV_CLK_PERI_I2S0,
+	CLK_CON_DIV_CLK_PERI_I2S1,
+	CLK_CON_DIV_CLK_PERI_PCLK,
+	CLK_CON_DIV_CLK_PERI_SPI,
+	CLK_CON_DIV_CLK_PERI_UART1,
+	CLK_CON_DIV_CLK_PERI_UART2,
+	CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS,
+	CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK,
+	CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK,
+	CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK,
+	CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI,
+	CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK,
+	CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART,
+	CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK,
+	CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART,
+	CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH,
+	CLK_CON_DMYQCH_CON_DMA4DSIM_QCH,
+	CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH,
+	CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH,
+};
+
+static const struct samsung_fixed_rate_clock peri_fixed_clks[] __initconst = {
+	FRATE(0, "clk_peri_audio", NULL, 0, 100000000),
+};
+
+PNAME(mout_peri_ip_user_p) = { "fin_pll", "dout_clkcmu_peri_ip" };
+PNAME(mout_peri_audio_user_p) = { "fin_pll", "dout_clkcmu_peri_audio" };
+PNAME(mout_peri_disp_user_p) = { "fin_pll", "dout_clkcmu_peri_disp" };
+PNAME(mout_peri_i2s0_p) = { "dout_peri_i2s0", "clk_peri_audio" };
+PNAME(mout_peri_i2s1_p) = { "dout_peri_i2s1", "clk_peri_audio" };
+
+static const struct samsung_mux_clock cmu_peri_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PERI_IP_USER, "mout_peri_ip_user", mout_peri_ip_user_p,
+	    PLL_CON0_MUX_CLK_PERI_IP_USER, 4, 1),
+	MUX(CLK_MOUT_PERI_AUDIO_USER, "mout_peri_audio_user",
+	    mout_peri_audio_user_p, PLL_CON0_MUX_CLK_PERI_AUDIO_USER, 4, 1),
+	MUX(CLK_MOUT_PERI_DISP_USER, "mout_peri_disp_user", mout_peri_disp_user_p,
+	    PLL_CON0_MUX_CLK_PERI_DISP_USER, 4, 1),
+	MUX(CLK_MOUT_PERI_I2S0, "mout_peri_i2s0", mout_peri_i2s0_p,
+	    CLK_CON_MUX_CLK_PERI_I2S0, 0, 1),
+	MUX(CLK_MOUT_PERI_I2S1, "mout_peri_i2s1", mout_peri_i2s1_p,
+	    CLK_CON_MUX_CLK_PERI_I2S1, 0, 1),
+};
+
+static const struct samsung_div_clock cmu_peri_div_clks[] __initconst = {
+	DIV(CLK_DOUT_PERI_SPI, "dout_peri_spi", "mout_peri_ip_user",
+	    CLK_CON_DIV_CLK_PERI_SPI, 0, 10),
+	DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "mout_peri_ip_user",
+	    CLK_CON_DIV_CLK_PERI_UART1, 0, 10),
+	DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "mout_peri_ip_user",
+	    CLK_CON_DIV_CLK_PERI_UART2, 0, 10),
+	DIV(CLK_DOUT_PERI_PCLK, "dout_peri_pclk", "mout_peri_ip_user",
+	    CLK_CON_DIV_CLK_PERI_PCLK, 0, 4),
+	DIV(CLK_DOUT_PERI_I2S0, "dout_peri_i2s0", "mout_peri_audio_user",
+	    CLK_CON_DIV_CLK_PERI_I2S0, 0, 4),
+	DIV(CLK_DOUT_PERI_I2S1, "dout_peri_i2s1", "mout_peri_audio_user",
+	    CLK_CON_DIV_CLK_PERI_I2S1, 0, 4),
+	DIV(CLK_DOUT_PERI_DSIM, "dout_peri_dsim", "mout_peri_disp_user",
+	    CLK_CON_DIV_CLK_PERI_DSIM, 0, 4),
+};
+
+static const struct samsung_gate_clock cmu_peri_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK, "dma4dsim_ipclkport_clk_apb_clk",
+	     "dout_peri_pclk", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST, "i2ssc0_ipclkport_clk_hst", "dout_peri_pclk",
+	     CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST, "i2ssc1_ipclkport_clk_hst", "dout_peri_pclk",
+	     CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK, "audio_out_ipclkport_clk",
+	     "mout_peri_audio_user", CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK, "peri_i2ssc0_ipclkport_clk", "mout_peri_i2s0",
+	     CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK, "peri_i2ssc1_ipclkport_clk", "mout_peri_i2s1",
+	     CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK, "dma4dsim_ipclkport_clk_axi_clk",
+	     "mout_peri_disp_user", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_GOUT_PERI_SPI0_SCLK_SPI, "peri_spi0_ipclkport_i_sclk_spi", "dout_peri_spi",
+	     CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_PERI_UART1_SCLK_UART, "uart1_sclk", "dout_peri_uart1",
+	     CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_PERI_UART2_SCLK_UART, "uart2_sclk", "dout_peri_uart2",
+	     CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, "apb_async_dsim_ipclkport_pclks",
+	     "dout_peri_pclk", CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, 21,
+	     CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK, "peri_i2c2_ipclkport_i_pclk", "dout_peri_pclk",
+	     CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK, "peri_i2c3_ipclkport_i_pclk", "dout_peri_pclk",
+	     CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_PERI_SPI0_PCLK, "peri_spi0_ipclkport_i_pclk", "dout_peri_pclk",
+	     CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_PERI_UART1_PCLK, "uart1_pclk", "dout_peri_pclk",
+	     CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_PERI_UART2_PCLK, "uart2_pclk", "dout_peri_pclk",
+	     CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info cmu_peri_info __initconst = {
+	.mux_clks		= cmu_peri_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmu_peri_mux_clks),
+	.div_clks		= cmu_peri_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmu_peri_div_clks),
+	.gate_clks              = cmu_peri_gate_clks,
+	.nr_gate_clks           = ARRAY_SIZE(cmu_peri_gate_clks),
+	.fixed_clks		= peri_fixed_clks,
+	.nr_fixed_clks		= ARRAY_SIZE(peri_fixed_clks),
+	.nr_clk_ids		= CMU_PERI_NR_CLK,
+	.clk_regs		= cmu_peri_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmu_peri_clk_regs),
+};
+
+/**
+ * artpec8_cmu_probe - Probe function for ARTPEC platform clocks
+ * @pdev: Pointer to platform device
+ *
+ * Configure clock hierarchy for clock domains of ARTPEC platform
+ */
+static int __init artpec8_cmu_probe(struct platform_device *pdev)
+{
+	const struct samsung_cmu_info *info;
+	struct device *dev = &pdev->dev;
+
+	info = of_device_get_match_data(dev);
+	exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+	return 0;
+}
+
+static const struct of_device_id artpec8_cmu_of_match[] = {
+	{
+		.compatible = "axis,artpec8-cmu-cmu",
+		.data = &cmu_cmu_info,
+	}, {
+		.compatible = "axis,artpec8-cmu-bus",
+		.data = &cmu_bus_info,
+	}, {
+		.compatible = "axis,artpec8-cmu-core",
+		.data = &cmu_core_info,
+	}, {
+		.compatible = "axis,artpec8-cmu-cpucl",
+		.data = &cmu_cpucl_info,
+	}, {
+		.compatible = "axis,artpec8-cmu-fsys",
+		.data = &cmu_fsys_info,
+	}, {
+		.compatible = "axis,artpec8-cmu-peri",
+		.data = &cmu_peri_info,
+	}, {
+	},
+};
+
+static struct platform_driver artpec8_cmu_driver __refdata = {
+	.driver	= {
+		.name = "artpec8-cmu",
+		.of_match_table = artpec8_cmu_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = artpec8_cmu_probe,
+};
+
+static int __init artpec8_cmu_init(void)
+{
+	return platform_driver_register(&artpec8_cmu_driver);
+}
+core_initcall(artpec8_cmu_init);
-- 
2.49.0

[PATCH v2 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC

[Ravi Patel]

From: SeonGu Kang <ksk4725@coasia.com>

Document the compatible string for ARTPEC-8 SoC pinctrl block,
which is similar to other Samsung SoC pinctrl blocks.

Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index de8460856141..9386dcd418c2 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -35,6 +35,7 @@ properties:
 
   compatible:
     enum:
+      - axis,artpec8-pinctrl
       - google,gs101-pinctrl
       - samsung,s3c2412-pinctrl
       - samsung,s3c2416-pinctrl
-- 
2.49.0

Re: [PATCH v2 04/10] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC

[Rob Herring (Arm)]

On Thu, 21 Aug 2025 18:02:48 +0530, Ravi Patel wrote:
> From: SeonGu Kang <ksk4725@coasia.com>
> 
> Document the compatible string for ARTPEC-8 SoC pinctrl block,
> which is similar to other Samsung SoC pinctrl blocks.
> 
> Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> ---
>  Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v2 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration

[Ravi Patel]

From: SeonGu Kang <ksk4725@coasia.com>

Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl.

Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 50 +++++++++++++++++++
 drivers/pinctrl/samsung/pinctrl-exynos.h      | 10 ++++
 drivers/pinctrl/samsung/pinctrl-samsung.c     |  2 +
 drivers/pinctrl/samsung/pinctrl-samsung.h     |  1 +
 4 files changed, 63 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index dd07720e32cc..ee3b488b00ff 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -76,6 +76,15 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off  = {
 	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
 };
 
+/*
+ * Bank type for non-alive type. Bit fields:
+ * CON: 4, DAT: 1, PUD: 4, DRV: 4
+ */
+static const struct samsung_pin_bank_type artpec_bank_type_off = {
+	.fld_width = { 4, 1, 4, 4, },
+	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
 /* Pad retention control code for accessing PMU regmap */
 static atomic_t exynos_shared_retention_refcnt;
 
@@ -1814,3 +1823,44 @@ const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
 	.ctrl		= gs101_pin_ctrl,
 	.num_ctrl	= ARRAY_SIZE(gs101_pin_ctrl),
 };
+
+/* pin banks of artpec8 pin-controller (FSYS0) */
+static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = {
+	ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00),
+	ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04),
+	ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08),
+	ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c),
+	ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10),
+	ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14),
+	ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18),
+	ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c),
+	ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20),
+	ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24),
+};
+
+/* pin banks of artpec8 pin-controller (PERIC) */
+static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = {
+	ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+	ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04),
+	ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+	ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c),
+};
+
+static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = {
+	{
+		/* pin-controller instance 0 FSYS data */
+		.pin_banks	= artpec8_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(artpec8_pin_banks0),
+		.eint_gpio_init	= exynos_eint_gpio_init,
+	}, {
+		/* pin-controller instance 1 PERIC data */
+		.pin_banks	= artpec8_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(artpec8_pin_banks1),
+		.eint_gpio_init	= exynos_eint_gpio_init,
+	},
+};
+
+const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = {
+	.ctrl		= artpec8_pin_ctrl,
+	.num_ctrl	= ARRAY_SIZE(artpec8_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index b483270ddc53..6bc04cb5ac9f 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -216,6 +216,16 @@
 		.name			= id				\
 	}
 
+#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs)			\
+	{								\
+		.type			= &artpec_bank_type_off,	\
+		.pctl_offset		= reg,				\
+		.nr_pins		= pins,				\
+		.eint_type		= EINT_TYPE_GPIO,		\
+		.eint_offset		= offs,				\
+		.name			= id				\
+	}
+
 /**
  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
  * generated by the external wakeup interrupt controller.
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 2896eb2de2c0..993efba5a9ad 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1468,6 +1468,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
 		.data = &s5pv210_of_data },
 #endif
 #ifdef CONFIG_PINCTRL_EXYNOS_ARM64
+	{ .compatible = "axis,artpec8-pinctrl",
+		.data = &artpec8_of_data },
 	{ .compatible = "google,gs101-pinctrl",
 		.data = &gs101_of_data },
 	{ .compatible = "samsung,exynos2200-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 3cf758df7d69..bfd88ad2f3ff 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -377,6 +377,7 @@ struct samsung_pmx_func {
 };
 
 /* list of all exported SoC specific data */
+extern const struct samsung_pinctrl_of_match_data artpec8_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
-- 
2.49.0

Re: [PATCH v2 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration

[Linus Walleij]

On Thu, Aug 21, 2025 at 2:40 PM Ravi Patel <ravi.patel@samsung.com> wrote:

> From: SeonGu Kang <ksk4725@coasia.com>
>
> Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl.
>
> Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com>
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>

Looks good to me.

I expect that Krzysztof will queue this and send
to me with a pull request once he's happy with it.

Yours,
Linus Walleij

[PATCH v2 06/10] dt-bindings: arm: Convert Axis board/soc bindings to json-schema

[Ravi Patel]

Convert Axis SoC bindings to DT schema format using json-schema.
Existing bindings supports ARTPEC-6 SoC and board.

Signed-off-by: SungMin Park <smn1196@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 .../devicetree/bindings/arm/axis.txt          | 13 ---------
 .../devicetree/bindings/arm/axis.yaml         | 29 +++++++++++++++++++
 2 files changed, 29 insertions(+), 13 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt
 create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml

diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt
deleted file mode 100644
index ebd33a88776f..000000000000
--- a/Documentation/devicetree/bindings/arm/axis.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Axis Communications AB
-ARTPEC series SoC Device Tree Bindings
-
-ARTPEC-6 ARM SoC
-================
-
-Required root node properties:
-- compatible = "axis,artpec6";
-
-ARTPEC-6 Development board:
----------------------------
-Required root node properties:
-- compatible = "axis,artpec6-dev-board", "axis,artpec6";
diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml
new file mode 100644
index 000000000000..610806d87416
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/axis.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/axis.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axis ARTPEC platforms
+
+maintainers:
+  - Jesper Nilsson <jesper.nilsson@axis.com>
+  - linux-arm-kernel@axis.com
+
+description: |
+  ARM platforms using SoCs designed by Axis branded as "ARTPEC".
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Axis ARTPEC-6 SoC board
+        items:
+          - enum:
+              - axis,artpec6-dev-board
+          - const: axis,artpec6
+
+additionalProperties: true
+
+...
--
2.49.0

Re: [PATCH v2 06/10] dt-bindings: arm: Convert Axis board/soc bindings to json-schema

[Rob Herring (Arm)]

On Thu, 21 Aug 2025 18:02:50 +0530, Ravi Patel wrote:
> Convert Axis SoC bindings to DT schema format using json-schema.
> Existing bindings supports ARTPEC-6 SoC and board.
> 
> Signed-off-by: SungMin Park <smn1196@coasia.com>
> Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> ---
>  .../devicetree/bindings/arm/axis.txt          | 13 ---------
>  .../devicetree/bindings/arm/axis.yaml         | 29 +++++++++++++++++++
>  2 files changed, 29 insertions(+), 13 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v2 07/10] dt-bindings: arm: axis: Add ARTPEC-8 grizzly board

[Ravi Patel]

From: SungMin Park <smn1196@coasia.com>

Document the Axis ARTPEC-8 SoC binding and the grizzly board
which uses ARTPEC-8 SoC.

Signed-off-by: SungMin Park <smn1196@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 Documentation/devicetree/bindings/arm/axis.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml
index 610806d87416..941eaed2b3cb 100644
--- a/Documentation/devicetree/bindings/arm/axis.yaml
+++ b/Documentation/devicetree/bindings/arm/axis.yaml
@@ -8,6 +8,7 @@ title: Axis ARTPEC platforms

 maintainers:
   - Jesper Nilsson <jesper.nilsson@axis.com>
+  - Lars Persson <lars.persson@axis.com>
   - linux-arm-kernel@axis.com

 description: |
@@ -24,6 +25,12 @@ properties:
               - axis,artpec6-dev-board
           - const: axis,artpec6

+      - description: Axis ARTPEC-8 SoC board
+        items:
+          - enum:
+              - axis,artpec8-grizzly
+          - const: axis,artpec8
+
 additionalProperties: true

 ...
--
2.49.0

Re: [PATCH v2 07/10] dt-bindings: arm: axis: Add ARTPEC-8 grizzly board

[Rob Herring (Arm)]

On Thu, 21 Aug 2025 18:02:51 +0530, Ravi Patel wrote:
> From: SungMin Park <smn1196@coasia.com>
> 
> Document the Axis ARTPEC-8 SoC binding and the grizzly board
> which uses ARTPEC-8 SoC.
> 
> Signed-off-by: SungMin Park <smn1196@coasia.com>
> Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> ---
>  Documentation/devicetree/bindings/arm/axis.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v2 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support

[Ravi Patel]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="Yes", Size: 13421 bytes --]

From: SungMin Park <smn1196@coasia.com>

Add initial device tree support for Axis ARTPEC-8 SoC.

This SoC contains 4 Cortex-A53 CPUs and several other peripheral IPs.

Signed-off-by: SungMin Park <smn1196@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 MAINTAINERS                                   |  12 +
 arch/arm64/Kconfig.platforms                  |   7 +
 arch/arm64/boot/dts/exynos/Makefile           |   1 +
 .../boot/dts/exynos/axis/artpec-pinctrl.h     |  36 +++
 .../boot/dts/exynos/axis/artpec8-pinctrl.dtsi | 120 +++++++++
 arch/arm64/boot/dts/exynos/axis/artpec8.dtsi  | 244 ++++++++++++++++++
 6 files changed, 420 insertions(+)
 create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
 create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
 create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 69511c3b2b76..956140fbf639 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3929,6 +3929,18 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/sound/axentia,*
 F:	sound/soc/atmel/tse850-pcm5142.c
 
+AXIS ARTPEC ARM64 SoC SUPPORT
+M:	Jesper Nilsson <jesper.nilsson@axis.com>
+M:	Lars Persson <lars.persson@axis.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	linux-samsung-soc@vger.kernel.org
+L:	linux-arm-kernel@axis.com
+S:	Maintained
+F:	Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml
+F:	arch/arm64/boot/dts/exynos/axis/
+F:	drivers/clk/samsung/clk-artpec*.c
+F:	include/dt-bindings/clock/axis,artpec*-clk.h
+
 AXI-FAN-CONTROL HARDWARE MONITOR DRIVER
 M:	Nuno Sá <nuno.sa@analog.com>
 L:	linux-hwmon@vger.kernel.org
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 8b76821f190f..48af8b154f7a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -40,6 +40,13 @@ config ARCH_APPLE
 	  This enables support for Apple's in-house ARM SoC family, such
 	  as the Apple M1.
 
+config ARCH_ARTPEC
+	bool "Axis Communications ARTPEC SoC Family"
+	depends on ARCH_EXYNOS
+	select ARM_GIC
+	help
+	   This enables support for the ARMv8 based ARTPEC SoC Family.
+
 menuconfig ARCH_BCM
 	bool "Broadcom SoC Support"
 
diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index f6f4bc650a94..c1a64cd29078 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+subdir-y += axis
 subdir-y += google
 
 dtb-$(CONFIG_ARCH_EXYNOS) += \
diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
new file mode 100644
index 000000000000..70bd1dcac85e
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Axis ARTPEC-8 SoC device tree pinctrl constants
+ *
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025  Axis Communications AB.
+ *             https://www.axis.com
+ */
+
+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
+#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
+
+#define ARTPEC_PIN_PULL_NONE		0
+#define ARTPEC_PIN_PULL_DOWN		1
+#define ARTPEC_PIN_PULL_UP		3
+
+#define ARTPEC_PIN_FUNC_INPUT		0
+#define ARTPEC_PIN_FUNC_OUTPUT		1
+#define ARTPEC_PIN_FUNC_2		2
+#define ARTPEC_PIN_FUNC_3		3
+#define ARTPEC_PIN_FUNC_4		4
+#define ARTPEC_PIN_FUNC_5		5
+#define ARTPEC_PIN_FUNC_6		6
+#define ARTPEC_PIN_FUNC_EINT		0xf
+#define ARTPEC_PIN_FUNC_F		ARTPEC_PIN_FUNC_EINT
+
+/* Drive strength for ARTPEC */
+#define ARTPEC_PIN_DRV_SR1		0x8
+#define ARTPEC_PIN_DRV_SR2		0x9
+#define ARTPEC_PIN_DRV_SR3		0xa
+#define ARTPEC_PIN_DRV_SR4		0xb
+#define ARTPEC_PIN_DRV_SR5		0xc
+#define ARTPEC_PIN_DRV_SR6		0xd
+
+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */
diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
new file mode 100644
index 000000000000..8d239a70f1b4
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025  Axis Communications AB.
+ *             https://www.axis.com
+ */
+
+#include "artpec-pinctrl.h"
+
+&pinctrl_fsys {
+	gpe0: gpe0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpe1: gpe1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpe2: gpe2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf0: gpf0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf1: gpf1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf2: gpf2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf3: gpf3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf4: gpf4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gps0: gps0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gps1: gps1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	serial0_bus: serial0-bus-pins {
+		samsung,pins = "gpf4-4", "gpf4-5";
+		samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
+		samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
+		samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
+	};
+};
+
+&pinctrl_peric {
+	gpa0: gpa0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpa1: gpa1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpa2: gpa2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpk0: gpk0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi
new file mode 100644
index 000000000000..8ee20bf4f680
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Axis ARTPEC-8 SoC device tree source
+ *
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025  Axis Communications AB.
+ *             https://www.axis.com
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axis,artpec8-clk.h>
+
+/ {
+	compatible = "axis,artpec8";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		pinctrl0 = &pinctrl_fsys;
+		pinctrl1 = &pinctrl_peric;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			enable-method = "psci";
+			cpu-idle-states = <&cpu_sleep>;
+			clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>;
+			clock-names = "cpu";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			enable-method = "psci";
+			cpu-idle-states = <&cpu_sleep>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			enable-method = "psci";
+			cpu-idle-states = <&cpu_sleep>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			enable-method = "psci";
+			cpu-idle-states = <&cpu_sleep>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_sleep: cpu-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <300>;
+				exit-latency-us = <1200>;
+				min-residency-us = <2000>;
+			};
+		};
+	};
+
+	fin_pll: clock-finpll {
+		compatible = "fixed-factor-clock";
+		clocks = <&osc_clk>;
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clock-output-names = "fin_pll";
+	};
+
+	osc_clk: clock-osc {
+		/* XXTI */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "osc_clk";
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0x0 0x0 0x0 0x17000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cmu_imem: clock-controller@10010000 {
+			compatible = "axis,artpec8-cmu-imem";
+			reg = <0x10010000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>,
+				 <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>;
+			clock-names = "fin_pll", "aclk", "jpeg";
+		};
+
+		timer@10040000 {
+			compatible = "axis,artpec8-mct", "samsung,exynos4210-mct";
+			reg = <0x10040000 0x1000>;
+			clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>;
+			clock-names = "fin_pll", "mct";
+			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		gic: interrupt-controller@10201000 {
+			compatible = "arm,gic-400";
+			reg = <0x10201000 0x1000>,
+			      <0x10202000 0x2000>,
+			      <0x10204000 0x2000>,
+			      <0x10206000 0x2000>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		cmu_cpucl: clock-controller@11410000 {
+			compatible = "axis,artpec8-cmu-cpucl";
+			reg = <0x11410000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>;
+			clock-names = "fin_pll", "switch";
+		};
+
+		cmu_cmu: clock-controller@12400000 {
+			compatible = "axis,artpec8-cmu-cmu";
+			reg = <0x12400000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>;
+			clock-names = "fin_pll";
+		};
+
+		cmu_core: clock-controller@12410000 {
+			compatible = "axis,artpec8-cmu-core";
+			reg = <0x12410000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>,
+				 <&cmu_cmu CLK_DOUT_CMU_CORE_DLP>;
+			clock-names = "fin_pll", "main", "dlp";
+		};
+
+		cmu_bus: clock-controller@12c10000 {
+			compatible = "axis,artpec8-cmu-bus";
+			reg = <0x12c10000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu CLK_DOUT_CMU_BUS>,
+				 <&cmu_cmu CLK_DOUT_CMU_BUS_DLP>;
+			clock-names = "fin_pll", "bus", "dlp";
+		};
+
+		cmu_peri: clock-controller@16410000 {
+			compatible = "axis,artpec8-cmu-peri";
+			reg = <0x16410000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu CLK_DOUT_CMU_PERI_IP>,
+				 <&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>,
+				 <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>;
+			clock-names = "fin_pll", "ip", "audio", "disp";
+		};
+
+		pinctrl_peric: pinctrl@165f0000 {
+			compatible = "axis,artpec8-pinctrl";
+			reg = <0x165f0000 0x1000>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		cmu_fsys: clock-controller@16c10000 {
+			compatible = "axis,artpec8-cmu-fsys";
+			reg = <0x16c10000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&fin_pll>,
+				 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
+				 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
+				 <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
+				 <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
+			clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
+		};
+
+		pinctrl_fsys: pinctrl@16c30000 {
+			compatible = "axis,artpec8-pinctrl";
+			reg = <0x16c30000 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		serial_0: serial@16cc0000 {
+			compatible = "axis,artpec8-uart";
+			reg = <0x16cc0000 0x100>;
+			clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>,
+				 <&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>;
+			clock-names = "uart", "clk_uart_baud0";
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&serial0_bus>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
-- 
2.49.0

Re: [PATCH v2 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support

[Krzysztof Kozlowski]

On 21/08/2025 14:32, Ravi Patel wrote:
> From: SungMin Park <smn1196@coasia.com>
> 
> Add initial device tree support for Axis ARTPEC-8 SoC.
> 
> This SoC contains 4 Cortex-A53 CPUs and several other peripheral IPs.
> 
> Signed-off-by: SungMin Park <smn1196@coasia.com>
> Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
...

> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

No CPU mask?

> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +};


Best regards,
Krzysztof

RE: [PATCH v2 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support

[Ravi Patel]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 22 August 2025 12:09
> To: Ravi Patel <ravi.patel@samsung.com>; jesper.nilsson@axis.com; mturquette@baylibre.com; sboyd@kernel.org;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com;
> alim.akhtar@samsung.com; linus.walleij@linaro.org; tomasz.figa@gmail.com; catalin.marinas@arm.com; will@kernel.org;
> arnd@arndb.de
> Cc: ksk4725@coasia.com; kenkim@coasia.com; pjsin865@coasia.com; gwk1013@coasia.com; hgkim05@coasia.com;
> mingyoungbo@coasia.com; smn1196@coasia.com; pankaj.dubey@samsung.com; shradha.t@samsung.com;
> inbaraj.e@samsung.com; swathi.ks@samsung.com; hrishikesh.d@samsung.com; dj76.yang@samsung.com;
> hypmean.kim@samsung.com; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; linux-arm-kernel@axis.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> gpio@vger.kernel.org; soc@lists.linux.dev
> Subject: Re: [PATCH v2 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support
> 
> On 21/08/2025 14:32, Ravi Patel wrote:
> > From: SungMin Park <smn1196@coasia.com>
> >
> > Add initial device tree support for Axis ARTPEC-8 SoC.
> >
> > This SoC contains 4 Cortex-A53 CPUs and several other peripheral IPs.
> >
> > Signed-off-by: SungMin Park <smn1196@coasia.com>
> > Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
> > Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
> ...
> 
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> 
> No CPU mask?

Thanks for review and pointing out.

Yes. You are right.
I will add GIC_CPU_MASK_SIMPLE(4) in next version as this uses GICv2 (gic-400) not GICv3.

This may be carried out from other exynos/fsd platforms

I found below 2 related links.
https://lkml.org/lkml/2025/6/13/1073
https://lkml.org/lkml/2023/11/28/403

Thanks,
Ravi

> 
> > +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +};
> 
> 
> Best regards,
> Krzysztof

[PATCH v2 09/10] arm64: dts: axis: Add ARTPEC-8 Grizzly dts support

[Ravi Patel]

From: SeonGu Kang <ksk4725@coasia.com>

Add initial devcie tree for the ARTPEC-8 Grizzly board.
The ARTPEC-8 Grizzly is a small board developed by Axis,
based on the Axis ARTPEC-8 SoC.

Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 arch/arm64/boot/dts/exynos/axis/Makefile      |  4 +++
 .../boot/dts/exynos/axis/artpec8-grizzly.dts  | 35 +++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 arch/arm64/boot/dts/exynos/axis/Makefile
 create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts

diff --git a/arch/arm64/boot/dts/exynos/axis/Makefile b/arch/arm64/boot/dts/exynos/axis/Makefile
new file mode 100644
index 000000000000..ccf00de64016
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/axis/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+dtb-$(CONFIG_ARCH_ARTPEC) += \
+	artpec8-grizzly.dtb
diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts
new file mode 100644
index 000000000000..5ae864ec3193
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Axis ARTPEC-8 Grizzly board device tree source
+ *
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025  Axis Communications AB.
+ *             https://www.axis.com
+ */
+
+/dts-v1/;
+#include "artpec8.dtsi"
+#include "artpec8-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
+	model = "ARTPEC-8 grizzly board";
+	compatible = "axis,artpec8-grizzly", "axis,artpec8";
+
+	aliases {
+		serial0 = &serial_0;
+	};
+
+	chosen {
+		stdout-path = &serial_0;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+};
+
+&osc_clk {
+	clock-frequency = <50000000>;
+};
--
2.49.0

[PATCH v2 10/10] arm64: defconfig: Enable Axis ARTPEC SoC

[Ravi Patel]

From: SungMin Park <smn1196@coasia.com>

Enable the Axis ARTPEC-8 SoC in arm64 defconfig.

Signed-off-by: SungMin Park <smn1196@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5bb8f09422a2..f94c1357d6f5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
 CONFIG_ARCH_APPLE=y
+CONFIG_ARCH_ARTPEC=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM2835=y
 CONFIG_ARCH_BCM_IPROC=y
-- 
2.49.0

Re: [PATCH v2 00/10] Add support for the Axis ARTPEC-8 SoC

[Krzysztof Kozlowski]

On 21/08/2025 14:32, Ravi Patel wrote:
> 
> Link to v1: https://lore.kernel.org/all/20250710002047.1573841-1-ksk4725@coasia.com/
> NOTE: The first version has been sent by Coasia.
>       After that, it has been agreed between Coasia and Samsung that Samsung will take
>       ownership of upstreaming ARTPEC-8 and ARTPEC-9 platforms.

Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets.

Best regards,
Krzysztof

RE: [PATCH v2 00/10] Add support for the Axis ARTPEC-8 SoC

[Ravi Patel]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 22 August 2025 11:56
> To: Ravi Patel <ravi.patel@samsung.com>; jesper.nilsson@axis.com; mturquette@baylibre.com; sboyd@kernel.org;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com;
> alim.akhtar@samsung.com; linus.walleij@linaro.org; tomasz.figa@gmail.com; catalin.marinas@arm.com; will@kernel.org;
> arnd@arndb.de
> Cc: ksk4725@coasia.com; kenkim@coasia.com; pjsin865@coasia.com; gwk1013@coasia.com; hgkim05@coasia.com;
> mingyoungbo@coasia.com; smn1196@coasia.com; pankaj.dubey@samsung.com; shradha.t@samsung.com;
> inbaraj.e@samsung.com; swathi.ks@samsung.com; hrishikesh.d@samsung.com; dj76.yang@samsung.com;
> hypmean.kim@samsung.com; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; linux-arm-kernel@axis.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> gpio@vger.kernel.org; soc@lists.linux.dev
> Subject: Re: [PATCH v2 00/10] Add support for the Axis ARTPEC-8 SoC
> 
> On 21/08/2025 14:32, Ravi Patel wrote:
> >
> > Link to v1: https://lore.kernel.org/all/20250710002047.1573841-1-ksk4725@coasia.com/
> > NOTE: The first version has been sent by Coasia.
> >       After that, it has been agreed between Coasia and Samsung that Samsung will take
> >       ownership of upstreaming ARTPEC-8 and ARTPEC-9 platforms.
> 
> Do not attach (thread) your patchsets to some other threads (unrelated
> or older versions). This buries them deep in the mailbox and might
> interfere with applying entire sets.

Sure, I will remove "--in-reply-to" while sending next version.

Thanks,
Ravi

> 
> Best regards,
> Krzysztof