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* [GIT PULL] clk: renesas: Updates for v6.17 (take two)
@ 2025-07-09 20:14 Geert Uytterhoeven
  2025-07-13 16:37 ` Stephen Boyd
  0 siblings, 1 reply; 2+ messages in thread
From: Geert Uytterhoeven @ 2025-07-09 20:14 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd
  Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven

	Hi Mike, Stephen,

The following changes since commit b7c26cbd5b704a350b3176669f47047153903bc9:

  clk: renesas: rzv2h: Add missing include file (2025-06-26 16:28:50 +0200)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.17-tag2

for you to fetch changes up to 0ab2d84f94dae48c3e7605cdc99dbb4e7c7b206a:

  clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well (2025-07-08 11:36:16 +0200)

----------------------------------------------------------------
clk: renesas: Updates for v6.17 (take two)

  - Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on
    RZ/V2H(P) and RZ/V2N,
  - Add SPI (RSPI) clocks and resets on RZ/V2H(P),
  - Add SDHI and I2C clocks on RZ/T2H and RZ/N2H,
  - Add Ethernet clocks and resets on RZ/G3E,
  - Miscellaneous fixes and improvements.

Note that this includes DT binding definition updates for the RZ/N2H,
RZ/T2H, RZ/V2H, and RZ/V2N SoCs, which are shared by clock driver and DT
source files.

Thanks for pulling!

----------------------------------------------------------------
Claudiu Beznea (1):
      clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well

Fabrizio Castro (1):
      clk: renesas: r9a09g057: Add entries for the RSPIs

Geert Uytterhoeven (2):
      Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17
      Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17

John Madieu (1):
      clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs

Lad Prabhakar (10):
      dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
      dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
      clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
      clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
      clk: renesas: r9a09g077: Add RIIC module clocks
      clk: renesas: r9a09g056: Add support for xspi mux and divider
      clk: renesas: r9a09g057: Add support for xspi mux and divider
      clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
      clk: renesas: r9a09g056: Add XSPI clock/reset
      clk: renesas: r9a09g057: Add XSPI clock/reset

 drivers/clk/renesas/r9a08g045-cpg.c                |  6 +-
 drivers/clk/renesas/r9a09g047-cpg.c                | 64 +++++++++++++++
 drivers/clk/renesas/r9a09g056-cpg.c                | 37 ++++++++-
 drivers/clk/renesas/r9a09g057-cpg.c                | 63 +++++++++++++-
 drivers/clk/renesas/r9a09g077-cpg.c                | 15 +++-
 drivers/clk/renesas/rzv2h-cpg.c                    | 95 +++++++++++++++++++++-
 drivers/clk/renesas/rzv2h-cpg.h                    | 24 ++++++
 include/dt-bindings/clock/renesas,r9a09g056-cpg.h  |  1 +
 include/dt-bindings/clock/renesas,r9a09g057-cpg.h  |  1 +
 .../dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h |  1 +
 .../dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h |  1 +
 11 files changed, 297 insertions(+), 11 deletions(-)

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

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