[GIT PULL] clk: renesas: Updates for v7.1 (take two)

[Geert Uytterhoeven <geert+renesas@glider.be>]

	Hi Mike, Stephen,

The following changes since commit c8d5972a25408b1daf73653ccd5207fdfc80c964:

  clk: renesas: r9a09g056: Add clock and reset entries for RTC (2026-03-06 13:33:56 +0100)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v7.1-tag2

for you to fetch changes up to 77894661c00ab99053c9606f0f7ec673065f86ac:

  clk: renesas: Add support for RZ/G3L SoC (2026-03-26 19:45:48 +0100)

----------------------------------------------------------------
clk: renesas: Updates for v7.1 (take two)

  - Add SPI clocks and resets on RZ/G3E,
  - Add PCIe clocks and resets on RZ/V2N, RZ/V2H(P), and RZ/G3E,
  - Enable watchdog reset on RZ/N1D,
  - Remove clocks for watchdogs meant for other CPU cores on RZ/V2N,
  - Handle critical clock during system resume on RZ/G2L, RZ/G2UL, and
    RZ/G3S,
  - Add initial support for the RZ/G3L (R9A08G046) SoC,
  - Miscellaneous fixes and improvements.

Thanks for pulling!

----------------------------------------------------------------
Biju Das (7):
      clk: renesas: rzg2l: Add support for critical resets
      clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries
      clk: renesas: rzg2l: Add helper for mod clock enable/disable
      clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()
      clk: renesas: rzg2l: Re-enable critical module clocks during resume
      dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
      clk: renesas: Add support for RZ/G3L SoC

Fabrizio Castro (1):
      clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}

Geert Uytterhoeven (1):
      Merge tag 'renesas-r9a08g046-dt-binding-defs-tag1' into renesas-clk-for-v7.1

Herve Codina (Schneider Electric) (1):
      clk: renesas: r9a06g032: Enable watchdog reset sources

John Madieu (1):
      clk: renesas: r9a09g047: Add PCIe clocks and reset

Lad Prabhakar (2):
      clk: renesas: r9a09g056: Add PCIe clocks and reset
      clk: renesas: r9a09g057: Add PCIe clocks and reset

Rosen Penev (1):
      clk: renesas: cpg-mssr: Use struct_size() helper

Tommaso Merciai (1):
      clk: renesas: r9a09g047: Add entries for the RSPIs

 .../bindings/clock/renesas,rzg2l-cpg.yaml          |  40 ++-
 drivers/clk/renesas/Kconfig                        |   7 +-
 drivers/clk/renesas/Makefile                       |   1 +
 drivers/clk/renesas/r9a06g032-clocks.c             |   5 +-
 drivers/clk/renesas/r9a07g043-cpg.c                |   9 +
 drivers/clk/renesas/r9a07g044-cpg.c                |  13 +
 drivers/clk/renesas/r9a08g045-cpg.c                |   9 +
 drivers/clk/renesas/r9a08g046-cpg.c                | 153 +++++++++
 drivers/clk/renesas/r9a09g047-cpg.c                |  29 ++
 drivers/clk/renesas/r9a09g056-cpg.c                |  20 +-
 drivers/clk/renesas/r9a09g057-cpg.c                |   5 +
 drivers/clk/renesas/renesas-cpg-mssr.c             |   4 +-
 drivers/clk/renesas/rzg2l-cpg.c                    |  91 +++++-
 drivers/clk/renesas/rzg2l-cpg.h                    |   8 +
 include/dt-bindings/clock/renesas,r9a08g046-cpg.h  | 342 +++++++++++++++++++++
 15 files changed, 698 insertions(+), 38 deletions(-)
 create mode 100644 drivers/clk/renesas/r9a08g046-cpg.c
 create mode 100644 include/dt-bindings/clock/renesas,r9a08g046-cpg.h

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds