From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [GIT PULL] clk: renesas: Updates for v7.2
Date: Tue, 19 May 2026 12:36:18 +0200 [thread overview]
Message-ID: <cover.1779185560.git.geert+renesas@glider.be> (raw)
Hi Mike, Stephen,
The following changes since commit 254f49634ee16a731174d2ae34bc50bd5f45e731:
Linux 7.1-rc1 (2026-04-26 14:19:00 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v7.2-tag1
for you to fetch changes up to 4f42053949324867dc40d67829f18a01539e6322:
clk: renesas: r8a73a4: Add ZT/ZTR trace clocks (2026-05-15 11:30:51 +0200)
----------------------------------------------------------------
clk: renesas: Updates for v7.2
- Add Ethernet, GPIO, CPU core, watchdog, serial, I2C, sound, and SPI
clocks and resets on RZ/G3L,
- Add the timer (MTU3) clock on RZ/T2H and RZ/N2H,
- Add Coresight trace clocks on R-Mobile A1 and APE6,
- Add display clocks and resets on RZ/G3E,
- Miscellaneous fixes and improvements.
Note that this includes:
- DT binding definition updates for the R-Mobile A1 and APE6 SoCs,
which are shared by the clock subsystem and DT source files,
- RZ/G3E Clock Pulse Generator PLLDSI limits, which are shared by
clock and MIPI DSI driver source files.
Thanks for pulling!
----------------------------------------------------------------
Biju Das (13):
clk: renesas: rzg2l: Drop always-false check in rzg3s_cpg_pll_clk_recalc_rate()
clk: renesas: rzg2l: Add support for enabling PLLs
clk: renesas: r8a08g046: Add support for PLL6
clk: renesas: r9a08g046: Add GBETH clocks and resets
clk: renesas: r9a08g046: Add GPIO clocks/resets
clk: renesas: r9a08g046: Add CA55 core clocks
clk: renesas: r9a08g046: Add WDT clocks and reset
clk: renesas: r9a08g046: Add SCIF{1..5} clocks and resets
clk: renesas: r9a08g046: Add I2C clocks and resets
clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks
clk: renesas: r9a08g046: Add RSCI clocks and resets
clk: renesas: r9a08g046: Add SSIF-2 clocks and resets
clk: renesas: r9a08g046: Add RSPI clocks and resets
Cosmin Tanislav (1):
clk: renesas: r9a09g077: Add MTU3 module clock
Geert Uytterhoeven (6):
Merge tag 'renesas-r8a7740-dt-binding-defs-tag1' into renesas-clk-for-v7.2
Merge tag 'clk-renesas-rzg3e-plldsi-tag' into renesas-clk-for-v7.2
clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()
clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()
clk: renesas: cpg-mssr: Add number of clock cells check
Merge tag 'renesas-r8a73a4-dt-binding-defs-tag1' into renesas-clk-for-v7.2
Marek Vasut (4):
dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile A1
clk: renesas: r8a7740: Add ZT/ZTR trace clocks
dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6
clk: renesas: r8a73a4: Add ZT/ZTR trace clocks
Tommaso Merciai (8):
clk: renesas: rzv2h: Add PLLDSI clk mux support
clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK support
clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks
clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks
clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks
clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK
clk: renesas: r9a09g047: Add support for DSI clocks and resets
clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets
.../bindings/clock/renesas,cpg-clocks.yaml | 8 +-
drivers/clk/renesas/clk-r8a73a4.c | 2 +
drivers/clk/renesas/clk-r8a7740.c | 2 +
drivers/clk/renesas/r9a08g046-cpg.c | 358 +++++++++++++++++++++
drivers/clk/renesas/r9a09g047-cpg.c | 84 +++++
drivers/clk/renesas/r9a09g077-cpg.c | 1 +
drivers/clk/renesas/renesas-cpg-mssr.c | 3 +
drivers/clk/renesas/rzg2l-cpg.c | 68 +++-
drivers/clk/renesas/rzg2l-cpg.h | 11 +-
drivers/clk/renesas/rzv2h-cpg.c | 181 +++++++++++
drivers/clk/renesas/rzv2h-cpg.h | 12 +
include/dt-bindings/clock/r8a73a4-clock.h | 2 +
include/dt-bindings/clock/r8a7740-clock.h | 2 +
include/linux/clk/renesas.h | 20 ++
14 files changed, 747 insertions(+), 7 deletions(-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next reply other threads:[~2026-05-19 10:36 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-19 10:36 Geert Uytterhoeven [this message]
2026-05-29 1:49 ` [GIT PULL] clk: renesas: Updates for v7.2 Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cover.1779185560.git.geert+renesas@glider.be \
--to=geert+renesas@glider.be \
--cc=linux-clk@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox