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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH1PEPF0000AD7C.mail.protection.outlook.com (10.167.244.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.6 via Frontend Transport; Wed, 8 Jul 2026 07:19:08 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Wed, 8 Jul 2026 02:19:06 -0500 Received: from localhost (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41 via Frontend Transport; Wed, 8 Jul 2026 02:19:05 -0500 From: Michal Simek To: , , , CC: Brian Masney , Conor Dooley , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Shubhrajyoti Datta , Stephen Boyd , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , kishore Manne , "moderated list:ARM/ZYNQ ARCHITECTURE" , "open list:COMMON CLK FRAMEWORK" Subject: [PATCH v4 0/5] clock: versal-clk: Fix Versal NET clock binding and switch to CCF Date: Wed, 8 Jul 2026 09:18:47 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jIuro5HgLPkDxuvNavC5vrRlNOURw9/6XdQyc8LmA992mJ+a9eqRNDzKFZ3FW3uYtboZGvDsr4Mi9PZQXpCgtoQrvEzdnmz9MR4fmu8m6r8sv9VZLWS4H2MdQZkU5Y3SeaSjSPblqBoT4IbR72LMASmWd5TkmzFCHnmjSMSBncQHYGOnwq1BwfL3iNd3YExvzyr2SIiZ3u5DWrYLHeKYieaUjuENg0eizfn3/MvG7lwxDjMI1EFA6NRBKvefGh1pSc7bK26/mEw/JP9ni0mf/f+WAqh0/8O7EdnTum7OBClKzoQxzzEXRvGS7aWVMZdcEhT3+4yLB5xw0sExSPNo2CyxLgnvor+Xpe7ChdAWxMtCLdVwyqDi6n1mwQWWcPmFkSG/Dt8VmXQHxNpixBhY4h78zI4y2srnrFYusU1HoWJKjyagawOPp7RTIOeNGYZq X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2026 07:19:08.8856 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c690601d-850b-4ecd-8492-08dedcc133cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8779 This series fixes the Versal NET clock controller DT binding validation and switches the platform to use the firmware-based CCF clock interface. Patch 1 extracts zynqmp to own DT binding file. Patch 2 restructures the if/then conditions in the versal-clk binding schema so that xlnx,versal-net-clk is matched first before falling back to xlnx,versal-clk. This fixes false "too long" validation errors caused by both conditions matching simultaneously when the fallback compatible is present. A dedicated example for the Versal NET 3-clock configuration is added and all examples are split into separate blocks for independent validation. Patch 3 switches Versal NET from static fixed-clock definitions to the firmware-based clock interface, enabling proper clock management through platform firmware. DT macro headers for clocks, power domains and resets are added. Thanks, Michal Changes in v4: - simplify expression to [0-6][0-9] from 0[0-9||[1-6][0-9] - Update regex from previous patch - Also update firmware node to match xlnx,versal-firmware enforced by schema Changes in v3: - new patch in series - New patch in series - Cover change in zynqmp-firmware.yaml - Move clock-cells to be the last in the example - Remove comment around (Optional clock) which is obvious from schema itself - Move clock-cells to be the last property in the example - use 2 spaces for indentation in example to follow the same style which is already used - Add fixed tag - Remove interrupt from zynqmp-power - Versal NET is using event framework instead. No interrupt is required. - Remove unused GEM{0,1}_REF_{R,T}X macros - Update commit message - s/zynqmp/versal-net/ in subject - Update copyrights - Make all macro values lower case - Fix guarding macro names Changes in v2: - New patch in series - Split zynqmp-clk from versal-clk - Update logic without ZynqMP part in this file and have if/else only around min/maxItems - use clock- node name for fixed clocks - Reuse existing versal-net-clk.dtsi file Michal Simek (5): dt-bindings: firmware: xilinx: Add missing example for ZynqMP dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema dt-bindings: clock: versal-clk: Fix Versal NET clock validation arm64: versal-net: Switch Versal NET to firmware clock interface .../bindings/clock/xlnx,versal-clk.yaml | 93 ++--- .../bindings/clock/xlnx,zynqmp-clk.yaml | 68 ++++ .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 15 +- .../arm64/boot/dts/xilinx/versal-net-clk.dtsi | 345 +++++++++++++----- arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h | 123 +++++++ .../boot/dts/xilinx/xlnx-versal-net-clk.h | 74 ++++ .../boot/dts/xilinx/xlnx-versal-net-power.h | 38 ++ .../boot/dts/xilinx/xlnx-versal-net-resets.h | 53 +++ .../arm64/boot/dts/xilinx/xlnx-versal-power.h | 55 +++ .../boot/dts/xilinx/xlnx-versal-resets.h | 106 ++++++ 10 files changed, 797 insertions(+), 173 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h --- base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482 branch: xnext/versal-net -- 2.43.0