[PATCH 0/5] clk: socfpga: add Agilex72 clock manager support

[evon.chiam@altera.com]

From: "Chiam, Evon" <evon.chiam@altera.com>

This series adds Clock Manager support for the Altera SoCFPGA Agilex72
platform. It also moves the Agilex72 device trees under dts/altera and
switches the board/SoC compatible strings to the "altr" vendor prefix,
matching Agilex7m and vendor-prefixes.yaml.

The Agilex72 clock manager exposes multiple register regions (clkmgr and
three GPPLLs) and provides the peripheral clocks used by the SoC. The
driver registers the PLL, peripheral, and gate clock tree, while the DT
describes the external input references and the clock manager node.

Patch summary:
  1/5: Fix Agilex72 compatible strings in the altera DT binding
  2/5: Add Agilex72 clock manager DT binding and clock ID header
  3/5: Add Agilex72 clock manager driver
  4/5: Move Agilex72 DT from dts/intel to dts/altera and use altr
  5/5: Add clock manager and input clocks to the Agilex72 DT

Chiam, Evon (5):
  dt-bindings: arm: altera: fix Agilex72 compatible vendor prefix
  dt-bindings: clock: altr,agilex72-clkmgr: add Agilex72 clock manager
    binding
  clk: socfpga: agilex72: add clock manager driver for Agilex72
  arm64: dts: altera: move Agilex72 DT and use altr prefix
  arm64: dts: altera: agilex72: add clock manager support

 .../devicetree/bindings/arm/altera.yaml       |    4 +-
 .../bindings/clock/altr,agilex72-clkmgr.yaml  |   86 ++
 MAINTAINERS                                   |    5 +
 arch/arm64/boot/dts/altera/Makefile           |    3 +-
 .../{intel => altera}/socfpga_agilex72.dtsi   |   48 +-
 .../socfpga_agilex72_socdk.dts                |   14 +-
 arch/arm64/boot/dts/intel/Makefile            |    1 -
 drivers/clk/socfpga/Kconfig                   |    3 +-
 drivers/clk/socfpga/Makefile                  |    2 +-
 drivers/clk/socfpga/clk-agilex72.c            | 1181 +++++++++++++++++
 drivers/clk/socfpga/clk-agilex72.h            |   91 ++
 .../dt-bindings/clock/altr,agilex72-clkmgr.h  |  116 ++
 12 files changed, 1542 insertions(+), 12 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/altr,agilex72-clkmgr.yaml
 rename arch/arm64/boot/dts/{intel => altera}/socfpga_agilex72.dtsi (74%)
 rename arch/arm64/boot/dts/{intel => altera}/socfpga_agilex72_socdk.dts (63%)
 create mode 100644 drivers/clk/socfpga/clk-agilex72.c
 create mode 100644 drivers/clk/socfpga/clk-agilex72.h
 create mode 100644 include/dt-bindings/clock/altr,agilex72-clkmgr.h

-- 
2.43.7