From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Marek Vasut <marex@denx.de>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH v5 0/2] clk: rs9: Fix and of_clk_hw_onecell_get() conversion
Date: Thu, 3 Sep 2026 12:09:24 +0200 [thread overview]
Message-ID: <cover.1788429994.git.geert+renesas@glider.be> (raw)
Hi all,
This patch series contains a fix and further development for the Renesas
9-series PCIe clock generator driver, which were submitted before as
separate patches As the fix hasn't been picked up yet, and the further
development depends on the fix, I am resending them as a series.
Changes compared to v4[1]:
- Add Reviewed-by.
Thanks for your comments!
[1] "[PATCH v4 0/2] clk: rs9: Fix and of_clk_hw_onecell_get() conversion"
https://lore.kernel.org/r/cover.1773241119.git.geert+renesas@glider.be
Geert Uytterhoeven (2):
clk: rs9: Add clock index range check to rs9_of_clk_get()
clk: rs9: Convert to clk_hw_onecell_data and of_clk_hw_onecell_get()
drivers/clk/clk-renesas-pcie.c | 39 ++++++++++++++++------------------
1 file changed, 18 insertions(+), 21 deletions(-)
--
2.43.0
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next reply other threads:[~2026-09-03 10:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 10:09 Geert Uytterhoeven [this message]
2026-09-03 10:09 ` [PATCH v5 1/2] clk: rs9: Add clock index range check to rs9_of_clk_get() Geert Uytterhoeven
2026-09-03 10:23 ` sashiko-bot
2026-09-03 10:09 ` [PATCH v5 2/2] clk: rs9: Convert to clk_hw_onecell_data and of_clk_hw_onecell_get() Geert Uytterhoeven
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