Re: [PATCH v1 5/5] clk: samsung: introduce exynos8890 clock driver

Peng Fan
2025-09-15T10:32:44Z

On Mon, Sep 15, 2025 at 11:59:47AM +0300, Ivaylo Ivanov wrote:
>On 9/15/25 10:49, Peng Fan wrote:
>> On Sun, Sep 14, 2025 at 03:21:16PM +0300, Ivaylo Ivanov wrote:
>>> Introduce a clocks management driver for exynos8890, providing clocks
>>> for the peripherals of that SoC.
>>>
>>> As exynos8890 is the first SoC to have HWACG, it differs a bit from the
>> Hardware Auto Clock Gating(HWACG), if I understand correctly.
>>
>>> newer SoCs. Q-channel and Q-state bits are separate registers, unlike
>>> the CLK_CON_GAT_* ones that feature HWACG bits in the same register
>>> that controls manual gating. Hence, don't use the clk-exynos-arm64
>>> helper, but implement logic that enforces manual gating according to
>>> how HWACG is implemented here.
>>>
>>> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
>>> ---
>>> drivers/clk/samsung/Makefile | 1 +
>>> drivers/clk/samsung/clk-exynos8890.c | 8695 ++++++++++++++++++++++++++
>>> 2 files changed, 8696 insertions(+)
>>> create mode 100644 drivers/clk/samsung/clk-exynos8890.c
>>>
>>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>>> index b77fe288e..982dc7c64 100644
>>> --- a/drivers/clk/samsung/Makefile
>>> +++ b/drivers/clk/samsung/Makefile
>>> @@ -22,6 +22,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7870.o
>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
>>> +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8890.o
>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos990.o
>>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
>>> diff --git a/drivers/clk/samsung/clk-exynos8890.c b/drivers/clk/samsung/clk-exynos8890.c
>>> new file mode 100644
>>> index 000000000..670587bae
>>> --- /dev/null
>>> +++ b/drivers/clk/samsung/clk-exynos8890.c
>>> @@ -0,0 +1,8695 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (C) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
>>> + * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
>>> + *
>>> + * Common Clock Framework support for Exynos8890 SoC.
>>> + */
>>> +
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/mod_devicetable.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +
>>> +#include <dt-bindings/clock/samsung,exynos8890-cmu.h>
>>> +
>>> +#include "clk.h"
>>> +
>>> +/* NOTE: Must be equal to the last clock ID increased by one */
>>> +#define TOP_NR_CLK (CLK_GOUT_TOP_SCLK_PROMISE_DISP + 1)
>>> +#define PERIS_NR_CLK (CLK_GOUT_PERIS_SCLK_PROMISE_PERIS + 1)
>>> +#define APOLLO_NR_CLK (CLK_GOUT_APOLLO_SCLK_PROMISE_APOLLO + 1)
>>> +#define AUD_NR_CLK (CLK_GOUT_AUD_SCLK_I2S_BCLK + 1)
>>> +#define BUS0_NR_CLK (CLK_GOUT_BUS0_ACLK_TREX_P_BUS0 + 1)
>>> +#define BUS1_NR_CLK (CLK_GOUT_BUS1_ACLK_TREX_P_BUS1 + 1)
>>> +#define CCORE_NR_CLK (CLK_GOUT_CCORE_SCLK_PROMISE + 1)
>>> +#define DISP0_NR_CLK (CLK_GOUT_DISP0_OSCCLK_DP_I_CLK_24M + 1)
>>> +#define DISP1_NR_CLK (CLK_GOUT_DISP1_SCLK_PROMISE_DISP1 + 1)
>>> +#define FSYS0_NR_CLK (CLK_GOUT_FSYS0_SCLK_USBHOST20_REF_CLK + 1)
>>> +#define FSYS1_NR_CLK (CLK_GOUT_FSYS1_SCLK_PROMISE_FSYS1 + 1)
>>> +#define G3D_NR_CLK (CLK_GOUT_G3D_SCLK_ASYNCAXI_G3D + 1)
>>> +#define MIF0_NR_CLK (CLK_GOUT_MIF0_RCLK_DREX + 1)
>>> +#define MIF1_NR_CLK (CLK_GOUT_MIF1_RCLK_DREX + 1)
>>> +#define MIF2_NR_CLK (CLK_GOUT_MIF2_RCLK_DREX + 1)
>>> +#define MIF3_NR_CLK (CLK_GOUT_MIF3_RCLK_DREX + 1)
>>> +#define MNGS_NR_CLK (CLK_GOUT_MNGS_SCLK_PROMISE0_MNGS + 1)
>>> +#define PERIC0_NR_CLK (CLK_GOUT_PERIC0_SCLK_PWM + 1)
>>> +#define PERIC1_NR_CLK (CLK_GOUT_PERIC1_SCLK_UART5 + 1)
>>> +
>>> +/*
>>> + * As exynos8890 first introduced hwacg, cmu registers are mapped similarly
>>> + * to exynos7, with the exception of the new q-state and q-ch registers that
>>> + * can set the behavior of automatic gates.
>>> + */
>>> +
>>> +/* decoded magic number from downstream */
>>> +#define QCH_EN_MASK BIT(0)
>>> +#define QCH_MASK (GENMASK(19, 16) | BIT(12))
>>> +#define QCH_DIS (QCH_MASK | FIELD_PREP(QCH_EN_MASK, 0))
>> Nit: align code.
>
>Aligned in my editor, patch files offset each line with a single symbol
>so formatting gets broken...

seems something broken in my mutt. Sorry for false alarm.

>> will not able to support GKI.
>>
>> It would be better to update to use platform drivers.
>
>Same as what Krzysztof said, design choice accross all samsung clock drivers.

Sure. No problem.

Regards
Peng
>